Split out this functionality to enable a fast-clear optimization for
color miptrees in the next commit.
v2: Avoid the additional refactor (Jason).
---
src/mesa/drivers/dri/i965/brw_clear.c | 23 +++++------------------
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 22 ++++++++++++++++++++++
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 7 +++++++
3 files changed, 34 insertions(+), 18 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c
b/src/mesa/drivers/dri/i965/brw_clear.c
index 3d540d6d905..fdc31cd9b68 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -234,25 +234,12 @@ brw_fast_clear_depth(struct gl_context *ctx)
* state then simply updating the miptree fast clear value is sufficient
* to change their clear value.
*/
- if (devinfo->gen >= 10 && !same_clear_value) {
- /* Before gen10, it was enough to just update the clear value in the
- * miptree. But on gen10+, we let blorp update the clear value state
- * buffer when doing a fast clear. Since we are skipping the fast
- * clear here, we need to update the clear color ourselves.
+ if (!same_clear_value) {
+ /* BLORP updates the indirect clear color buffer when performing a
+ * fast clear. Since we are skipping the fast clear here, we need to
+ * do the update ourselves.
*/
- uint32_t clear_offset = mt->aux_buf->clear_color_offset;
- union isl_color_value clear_color = { .f32 = { clear_value, } };
-
- /* We can't update the clear color while the hardware is still using
- * the previous one for a resolve or sampling from it. So make sure
- * that there's no pending commands at this point.
- */
- brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL);
- for (int i = 0; i < 4; i++) {
- brw_store_data_imm32(brw, mt->aux_buf->clear_color_bo,
- clear_offset + i * 4, clear_color.u32[i]);
- }
- brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE);
+ intel_miptree_update_indirect_color(brw, mt);
}
return true;
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 93a91fd8081..1006635c0d7 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -3837,3 +3837,25 @@ intel_miptree_get_clear_color(const struct
gen_device_info *devinfo,
return mt->fast_clear_color;
}
}
+
+void
+intel_miptree_update_indirect_color(struct brw_context *brw,
+ struct intel_mipmap_tree *mt)
+{
+ assert(mt->aux_buf);
+
+ if (mt->aux_buf->clear_color_bo == NULL)
+ return;
+
+ /* We can't update the clear color while the hardware is still using the
+ * previous one for a resolve or sampling from it. Make sure that there are
+ * no pending commands at this point.
+ */
+ brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL);
+ for (int i = 0; i < 4; i++) {
+ brw_store_data_imm32(brw, mt->aux_buf->clear_color_bo,
+ mt->aux_buf->clear_color_offset + i * 4,
+ mt->fast_clear_color.u32[i]);
+ }
+ brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE);
+}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index e99ea44b809..1c2361c1cb0 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -749,6 +749,13 @@ intel_miptree_set_depth_clear_value(struct brw_context
*brw,
struct intel_mipmap_tree *mt,
float clear_value);
+/* If this miptree has an indirect clear color, update it with the value stored
+ * in the miptree object.
+ */
+void
+intel_miptree_update_indirect_color(struct brw_context *brw,
+ struct intel_mipmap_tree *mt);
+
#ifdef __cplusplus
}
#endif
--
2.16.2
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