This helper adds buffers created by the application to the
global BO list, while radv_cs_add_buffer() is called directly
for adding BOs created by the driver. This will allow us to
improve the global BO list path a little bit.
Because the priority is quite useless I removed the parameter.
Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
---
src/amd/vulkan/radv_cmd_buffer.c | 40 +++++++++++++---------------
src/amd/vulkan/radv_descriptor_set.c | 6 ++---
src/amd/vulkan/radv_meta_buffer.c | 8 +++---
src/amd/vulkan/radv_private.h | 13 +++++++++
4 files changed, 39 insertions(+), 28 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 72fb6d6357..412c35c1ca 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -839,13 +839,13 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer)
if (!pipeline->shaders[i])
continue;
- radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
- pipeline->shaders[i]->bo, 8);
+ radv_cmd_buffer_add_buffer(cmd_buffer,
+ pipeline->shaders[i]->bo);
}
if (radv_pipeline_has_gs(pipeline))
- radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
- pipeline->gs_copy_shader->bo, 8);
+ radv_cmd_buffer_add_buffer(cmd_buffer,
+ pipeline->gs_copy_shader->bo);
if (unlikely(cmd_buffer->device->trace_bo))
radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
@@ -1255,7 +1255,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer)
struct radv_image *image = att->attachment->image;
VkImageLayout layout = subpass->color_attachments[i].layout;
- radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
att->attachment->bo, 8);
+ radv_cmd_buffer_add_buffer(cmd_buffer, att->attachment->bo);
assert(att->attachment->aspect_mask &
VK_IMAGE_ASPECT_COLOR_BIT);
radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
@@ -1268,7 +1268,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer)
VkImageLayout layout = subpass->depth_stencil_attachment.layout;
struct radv_attachment_info *att =
&framebuffer->attachments[idx];
struct radv_image *image = att->attachment->image;
- radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
att->attachment->bo, 8);
+ radv_cmd_buffer_add_buffer(cmd_buffer, att->attachment->bo);
MAYBE_UNUSED uint32_t queue_mask =
radv_image_queue_family_mask(image,
cmd_buffer->queue_family_index,
cmd_buffer->queue_family_index);
@@ -2152,8 +2152,7 @@ void radv_CmdBindVertexBuffers(
vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
vb[idx].offset = pOffsets[i];
- radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
- vb[idx].buffer->bo, 8);
+ radv_cmd_buffer_add_buffer(cmd_buffer, vb[idx].buffer->bo);
}
if (!changed) {
@@ -2189,7 +2188,7 @@ void radv_CmdBindIndexBuffer(
int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
cmd_buffer->state.max_index_count = (index_buffer->size - offset) >>
index_size_shift;
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
- radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
index_buffer->bo, 8);
+ radv_cmd_buffer_add_buffer(cmd_buffer, index_buffer->bo);
}
@@ -2198,8 +2197,6 @@ radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer,
VkPipelineBindPoint bind_point,
struct radv_descriptor_set *set, unsigned idx)
{
- struct radeon_winsys *ws = cmd_buffer->device->ws;
-
radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
if (!set)
return;
@@ -2208,10 +2205,11 @@ radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer,
for (unsigned j = 0; j < set->layout->buffer_count; ++j)
if (set->descriptors[j])
- radv_cs_add_buffer(ws, cmd_buffer->cs,
set->descriptors[j], 7);
+ radv_cmd_buffer_add_buffer(cmd_buffer,
+ set->descriptors[j]);
if(set->bo)
- radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
+ radv_cmd_buffer_add_buffer(cmd_buffer, set->bo);
}
void radv_CmdBindDescriptorSets(
@@ -2425,8 +2423,8 @@ radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer)
MAX2(cmd_buffer->compute_scratch_size_needed,
pipeline->max_waves *
pipeline->scratch_bytes_per_wave);
- radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
- pipeline->shaders[MESA_SHADER_COMPUTE]->bo, 8);
+ radv_cmd_buffer_add_buffer(cmd_buffer,
+ pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
if (unlikely(cmd_buffer->device->trace_bo))
radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
@@ -3036,7 +3034,6 @@ radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
const struct radv_draw_info *info)
{
struct radv_cmd_state *state = &cmd_buffer->state;
- struct radeon_winsys *ws = cmd_buffer->device->ws;
struct radeon_winsys_cs *cs = cmd_buffer->cs;
if (info->indirect) {
@@ -3045,7 +3042,7 @@ radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
va += info->indirect->offset + info->indirect_offset;
- radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
+ radv_cmd_buffer_add_buffer(cmd_buffer, info->indirect->bo);
radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
radeon_emit(cs, 1);
@@ -3057,7 +3054,8 @@ radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
count_va += info->count_buffer->offset +
info->count_buffer_offset;
- radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
+ radv_cmd_buffer_add_buffer(cmd_buffer,
+ info->count_buffer->bo);
}
if (!state->subpass->view_mask) {
@@ -3421,7 +3419,7 @@ radv_emit_dispatch_packets(struct radv_cmd_buffer
*cmd_buffer,
va += info->indirect->offset + info->indirect_offset;
- radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
+ radv_cmd_buffer_add_buffer(cmd_buffer, info->indirect->bo);
if (loc->sgpr_idx != -1) {
for (unsigned i = 0; i < 3; ++i) {
@@ -3956,7 +3954,7 @@ static void write_event(struct radv_cmd_buffer
*cmd_buffer,
struct radeon_winsys_cs *cs = cmd_buffer->cs;
uint64_t va = radv_buffer_get_va(event->bo);
- radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
+ radv_cmd_buffer_add_buffer(cmd_buffer, event->bo);
MAYBE_UNUSED unsigned cdw_max =
radeon_check_space(cmd_buffer->device->ws, cs, 18);
@@ -4012,7 +4010,7 @@ void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
uint64_t va = radv_buffer_get_va(event->bo);
- radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
+ radv_cmd_buffer_add_buffer(cmd_buffer, event->bo);
MAYBE_UNUSED unsigned cdw_max =
radeon_check_space(cmd_buffer->device->ws, cs, 7);
diff --git a/src/amd/vulkan/radv_descriptor_set.c
b/src/amd/vulkan/radv_descriptor_set.c
index 4b08a1f0f8..bc03f5d3db 100644
--- a/src/amd/vulkan/radv_descriptor_set.c
+++ b/src/amd/vulkan/radv_descriptor_set.c
@@ -720,7 +720,7 @@ static void write_texel_buffer_descriptor(struct
radv_device *device,
memcpy(dst, buffer_view->state, 4 * 4);
if (cmd_buffer)
- radv_cs_add_buffer(device->ws, cmd_buffer->cs, buffer_view->bo,
7);
+ radv_cmd_buffer_add_buffer(cmd_buffer, buffer_view->bo);
else
*buffer_list = buffer_view->bo;
}
@@ -750,7 +750,7 @@ static void write_buffer_descriptor(struct radv_device
*device,
S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
if (cmd_buffer)
- radv_cs_add_buffer(device->ws, cmd_buffer->cs, buffer->bo, 7);
+ radv_cmd_buffer_add_buffer(cmd_buffer, buffer->bo);
else
*buffer_list = buffer->bo;
}
@@ -794,7 +794,7 @@ write_image_descriptor(struct radv_device *device,
memcpy(dst, descriptor, 16 * 4);
if (cmd_buffer)
- radv_cs_add_buffer(device->ws, cmd_buffer->cs, iview->bo, 7);
+ radv_cmd_buffer_add_buffer(cmd_buffer, iview->bo);
else
*buffer_list = iview->bo;
}
diff --git a/src/amd/vulkan/radv_meta_buffer.c
b/src/amd/vulkan/radv_meta_buffer.c
index 2e1ba2c7b2..373b4a52ea 100644
--- a/src/amd/vulkan/radv_meta_buffer.c
+++ b/src/amd/vulkan/radv_meta_buffer.c
@@ -415,7 +415,7 @@ uint32_t radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer,
} else if (size) {
uint64_t va = radv_buffer_get_va(bo);
va += offset;
- radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, bo,
8);
+ radv_cmd_buffer_add_buffer(cmd_buffer, bo);
si_cp_dma_clear_buffer(cmd_buffer, va, size, value);
}
@@ -438,8 +438,8 @@ void radv_copy_buffer(struct radv_cmd_buffer *cmd_buffer,
src_va += src_offset;
dst_va += dst_offset;
- radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
src_bo, 8);
- radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
dst_bo, 8);
+ radv_cmd_buffer_add_buffer(cmd_buffer, src_bo);
+ radv_cmd_buffer_add_buffer(cmd_buffer, dst_bo);
si_cp_dma_buffer_copy(cmd_buffer, src_va, dst_va, size);
}
@@ -506,7 +506,7 @@ void radv_CmdUpdateBuffer(
if (dataSize < RADV_BUFFER_OPS_CS_THRESHOLD) {
si_emit_cache_flush(cmd_buffer);
- radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
dst_buffer->bo, 8);
+ radv_cmd_buffer_add_buffer(cmd_buffer, dst_buffer->bo);
radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
words + 4);
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index dfe4c5f942..7c896b0d0e 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1037,6 +1037,19 @@ struct radv_cmd_buffer {
bool pending_reset_query;
};
+/**
+ * Add buffers created by the application to the global BO list.
+ */
+static inline void
+radv_cmd_buffer_add_buffer(struct radv_cmd_buffer *cmd_buffer,
+ struct radeon_winsys_bo *bo)
+{
+ struct radeon_winsys *ws = cmd_buffer->device->ws;
+ struct radeon_winsys_cs *cs = cmd_buffer->cs;
+
+ ws->cs_add_buffer(cs, bo, 8);
+}
+
struct radv_image;
bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
--
2.17.0
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
