On 12/04/18 09:36, Ian Romanick wrote:
Are we still calculating limits (that affect whether or not a shader can
successfully link) after only doing GLSL optimizations? I'm worried
that making a pretty big change to the optimization path is going to
break some app on (most likely) an older piece of hardware because the
linker will now determine that it exceeds some limit.
All tests pass for all i965 hardware on Jenkins (at least that's what
the result emails say :P I've been fooled before). I also have no
shader-db link errors on IVY bridge. Ideally we should move to a NIR
linker so we can avoid these issues and better eliminate unused uniforms
etc, I believe there is going to be some for of NIR linker coming with
the spirv support.
Anyway I'll let you guys decide if you want to turn on
GLSLOptimizeConservatively for i965 but I still want to land the rest of
the series so gallium drivers such as radeonsi/vc4 can make use of the
faster NIR passes.
On 04/09/2018 09:34 PM, Timothy Arceri wrote:
This series is part of an effort to reduce the regression in compile
times when switching radeonsi from TGIS -> NIR. But it also turns
out to be quite handy for i965 too.
The idea is to make better use of GLSLOptimizeConservatively.
Currently TGSI must ignore the flag until all functions have been
inlined by the GLSL IR opts. Since NIR can do function inlining we
can drop the post linking opts calls for Gallium drivers that use
NIR and just use the faster NIR opts instead. The patches to do
this will come in a follow-up series since it requires some
refactoring and testing and I wanted to get this out for review.
For i965 this series enables GLSLOptimizeConservatively for a nice
boost in compile times and very little change in shader-db.
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