Re: [Mesa-dev] [PATCH v4 08/18] intel/blorp: Update clear color state buffer during fast clears.

[Jordan Justen]

On 2018-03-08 08:49:01, Rafael Antognolli wrote:
> We always want to update the fast clear color during a fast clear on
> i965. On anv, we doing that before a resolve, but by adding support to

s/we/we are/ ?

Patches 5 - 9:
Reviewed-by: Jordan Justen <jordan.l.jus...@intel.com>

> blorp, we can do a similar thing and update it during a fast clear
> instead.
> 
> The goal is to remove some code from anv that does such update, and
> centralize everything in blorp, hopefully removing a lot of code
> duplication. It also allows us to have a similar behavior on gen < 9 and
> gen >= 10.
> 
> Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
> ---
>  src/intel/blorp/blorp_genX_exec.h | 48 
> +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 48 insertions(+)
> 
> diff --git a/src/intel/blorp/blorp_genX_exec.h 
> b/src/intel/blorp/blorp_genX_exec.h
> index c68767a2faa..eef6ed8291a 100644
> --- a/src/intel/blorp/blorp_genX_exec.h
> +++ b/src/intel/blorp/blorp_genX_exec.h
> @@ -1642,6 +1642,51 @@ blorp_emit_gen8_hiz_op(struct blorp_batch *batch,
>  }
>  #endif
>  
> +static void
> +blorp_update_clear_color(struct blorp_batch *batch,
> +                         const struct brw_blorp_surface_info *info,
> +                         enum isl_aux_op op)
> +{
> +   if (info->clear_color_addr.buffer && op == ISL_AUX_OP_FAST_CLEAR) {
> +#if GEN_GEN >= 9
> +      for (int i = 0; i < 4; i++) {
> +         blorp_emit(batch, GENX(MI_STORE_DATA_IMM), sdi) {
> +            sdi.Address = info->clear_color_addr;
> +            sdi.Address.offset += i * 4;
> +            sdi.ImmediateData = info->clear_color.u32[i];
> +         }
> +      }
> +#elif GEN_GEN >= 7
> +      blorp_emit(batch, GENX(MI_STORE_DATA_IMM), sdi) {
> +         sdi.Address = info->clear_color_addr;
> +         sdi.ImmediateData = ISL_CHANNEL_SELECT_RED   << 25 |
> +                             ISL_CHANNEL_SELECT_GREEN << 22 |
> +                             ISL_CHANNEL_SELECT_BLUE  << 19 |
> +                             ISL_CHANNEL_SELECT_ALPHA << 16;
> +         if (isl_format_has_int_channel(info->view.format)) {
> +            for (unsigned i = 0; i < 4; i++) {
> +               assert(info->clear_color.u32[i] == 0 ||
> +                      info->clear_color.u32[i] == 1);
> +            }
> +            sdi.ImmediateData |= (info->clear_color.u32[0] != 0) << 31;
> +            sdi.ImmediateData |= (info->clear_color.u32[1] != 0) << 30;
> +            sdi.ImmediateData |= (info->clear_color.u32[2] != 0) << 29;
> +            sdi.ImmediateData |= (info->clear_color.u32[3] != 0) << 28;
> +         } else {
> +            for (unsigned i = 0; i < 4; i++) {
> +               assert(info->clear_color.f32[i] == 0.0f ||
> +                      info->clear_color.f32[i] == 1.0f);
> +            }
> +            sdi.ImmediateData |= (info->clear_color.f32[0] != 0.0f) << 31;
> +            sdi.ImmediateData |= (info->clear_color.f32[1] != 0.0f) << 30;
> +            sdi.ImmediateData |= (info->clear_color.f32[2] != 0.0f) << 29;
> +            sdi.ImmediateData |= (info->clear_color.f32[3] != 0.0f) << 28;
> +         }
> +      }
> +#endif
> +   }
> +}
> +
>  /**
>   * \brief Execute a blit or render pass operation.
>   *
> @@ -1654,6 +1699,9 @@ blorp_emit_gen8_hiz_op(struct blorp_batch *batch,
>  static void
>  blorp_exec(struct blorp_batch *batch, const struct blorp_params *params)
>  {
> +   blorp_update_clear_color(batch, &params->dst, params->fast_clear_op);
> +   blorp_update_clear_color(batch, &params->depth, params->hiz_op);
> +
>  #if GEN_GEN >= 8
>     if (params->hiz_op != ISL_AUX_OP_NONE) {
>        blorp_emit_gen8_hiz_op(batch, params);
> -- 
> 2.14.3
> 
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