This doesn't work. Well, I mean, it sort-of works. At this point in the
series, it will break things because Vulkan will start copying 8 dwords
into your surface state and over-write the start of another surface state.
Later on, I'm sure it's all good because we no longer copy things around.
I haven't seen where you use it yet so I'm not sure what we should do.
On Wed, Feb 21, 2018 at 1:45 PM, Rafael Antognolli <
rafael.antogno...@intel.com> wrote:
> On gen10 and newer, there's a struct describing how to use the indirect
> clear color buffer, and it seems to be 8 dwords long - 4 for the clear
> color and the last 4 used by the hardware, apparently depending on the
> generation. So just set aside space for them since gen10.
>
> Optionally we can later add the struct to the genxml, though it wouldn't
> really be used for anything else other than calculating this size.
>
> [jordan.l.jus...@intel.com: isl_device_init changes]
> Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
> Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
> ---
> src/intel/isl/isl.c | 27 ++++++++++++++++++---------
> 1 file changed, 18 insertions(+), 9 deletions(-)
>
> diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
> index 1a32c028183..77641a89f86 100644
> --- a/src/intel/isl/isl.c
> +++ b/src/intel/isl/isl.c
> @@ -73,15 +73,24 @@ isl_device_init(struct isl_device *dev,
> dev->ss.size = RENDER_SURFACE_STATE_length(info) * 4;
> dev->ss.align = isl_align(dev->ss.size, 32);
>
> - dev->ss.clear_value_size =
> - isl_align(RENDER_SURFACE_STATE_RedClearColor_bits(info) +
> - RENDER_SURFACE_STATE_GreenClearColor_bits(info) +
> - RENDER_SURFACE_STATE_BlueClearColor_bits(info) +
> - RENDER_SURFACE_STATE_AlphaClearColor_bits(info), 32) / 8;
> -
> - dev->ss.clear_value_offset =
> - RENDER_SURFACE_STATE_RedClearColor_start(info) / 32 * 4;
> -
> + if (ISL_DEV_GEN(dev) >= 10) {
> + /* Clear Color structure
> + * - 4 dwords for the clear color
> + * - 2 dwords that can be used by the hardware for converted clear
> color
> + * + some extra bits.
> + */
> + dev->ss.clear_value_size = 8 * 4;
> + dev->ss.clear_value_offset =
> + RENDER_SURFACE_STATE_ClearValueAddress_start(info) / 32 * 4;
> + } else {
> + dev->ss.clear_value_size =
> + isl_align(RENDER_SURFACE_STATE_RedClearColor_bits(info) +
> + RENDER_SURFACE_STATE_GreenClearColor_bits(info) +
> + RENDER_SURFACE_STATE_BlueClearColor_bits(info) +
> + RENDER_SURFACE_STATE_AlphaClearColor_bits(info), 32)
> / 8;
> + dev->ss.clear_value_offset =
> + RENDER_SURFACE_STATE_RedClearColor_start(info) / 32 * 4;
> + }
> assert(RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info) % 8 == 0);
> dev->ss.addr_offset =
> RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info) / 8;
> --
> 2.14.3
>
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