Anuj Phogat <anuj.pho...@gmail.com> writes:
> On Wed, Feb 21, 2018 at 10:00 AM, Scott D Phillips
> <scott.d.phill...@intel.com> wrote:
>> Matt Turner <matts...@gmail.com> writes:
>>
>>> From: Anuj Phogat <anuj.pho...@intel.com>
>>>
>>> Signed-off-by: Anuj Phogat <anuj.pho...@intel.com>
>>> ---
>>> include/pci_ids/i965_pci_ids.h | 9 ++++++
>>> src/intel/common/gen_device_info.c | 56
>>> +++++++++++++++++++++++++++++++++++++-
>>> 2 files changed, 64 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
>>> index feb9c582b19..81c9a5f13fb 100644
>>> --- a/include/pci_ids/i965_pci_ids.h
>>> +++ b/include/pci_ids/i965_pci_ids.h
>>> @@ -196,3 +196,12 @@ CHIPSET(0x5A50, cnl_5x8, "Intel(R) HD Graphics
>>> (Cannonlake 5x8 GT2)")
>>> CHIPSET(0x5A51, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
>>> CHIPSET(0x5A52, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
>>> CHIPSET(0x5A54, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
>>> +CHIPSET(0x8A50, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
>>> +CHIPSET(0x8A51, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
>>> +CHIPSET(0x8A52, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
>>> +CHIPSET(0x8A5A, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
>>> +CHIPSET(0x8A5B, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
>>> +CHIPSET(0x8A5C, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
>>> +CHIPSET(0x8A5D, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
>>> +CHIPSET(0x8A71, icl_1x8, "Intel(R) HD Graphics (Ice Lake 1x8 GT0.5)")
>>> +CHIPSET(0xFF05, icl_8x8, "Intel(R) HD Graphics (Ice Lake Simulation)")
>>
>> Simulation should be removed.
>>
>>> diff --git a/src/intel/common/gen_device_info.c
>>> b/src/intel/common/gen_device_info.c
>>> index a08a13a32a4..8bf4b6b9bb0 100644
>>> --- a/src/intel/common/gen_device_info.c
>>> +++ b/src/intel/common/gen_device_info.c
>>> @@ -731,6 +731,49 @@ static const struct gen_device_info
>>> gen_device_info_cnl_5x8 = {
>>> .is_cannonlake = true,
>>> };
>>>
>>> +#define GEN11_HW_INFO \
>>> + .gen = 11, \
>>> + .has_pln = false, \
>>> + .max_vs_threads = 364, \
>>> + .max_gs_threads = 224, \
>>> + .max_tcs_threads = 224, \
>>> + .max_tes_threads = 364, \
>>> + .max_cs_threads = 56, \
>>> + .urb = { \
>>> + .size = 1024, \
>>> + .min_entries = { \
>>> + [MESA_SHADER_VERTEX] = 64, \
>>> + [MESA_SHADER_TESS_EVAL] = 34, \
>>> + }, \
>>> + .max_entries = { \
>>> + [MESA_SHADER_VERTEX] = 2384, \
>>> + [MESA_SHADER_TESS_CTRL] = 1032, \
>>> + [MESA_SHADER_TESS_EVAL] = 2384, \
>>> + [MESA_SHADER_GEOMETRY] = 1032, \
>>> + }, \
>>> + }
>>> +
>>> +#define GEN11_FEATURES(_gt, _slices, _l3) \
>>> + GEN8_FEATURES, \
>>> + GEN11_HW_INFO, \
>>> + .gt = _gt, .num_slices = _slices, .l3_banks = _l3
>>> +
>>> +static const struct gen_device_info gen_device_info_icl_8x8 = {
>>> + GEN11_FEATURES(2, 1, 8),
>>> +};
>>> +
>>> +static const struct gen_device_info gen_device_info_icl_6x8 = {
>>> + GEN11_FEATURES(1, 1, 6),
>>> +};
>>> +
>>> +static const struct gen_device_info gen_device_info_icl_4x8 = {
>>> + GEN11_FEATURES(1, 1, 6),
>>
>> Should be 1, 1, 4 right?
>>
>
> We don't have device attributes listed in the docs for this SKU :(. But,
> as I have understood number of subslices don't affect the number
> of banks. L3 banks are part of Slice common. e.g. 1x4x8 and
> 1x6x8 have the same number of L3 banks.
Right you are, my mistake, the l3_banks look right. What I meant to note
was that the num_subslices isn't being set by this (the way we do for
gen10). Shouldn't it be like:
#define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
GEN8_FEATURES, \
GEN11_HW_INFO, \
.gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
.num_subslices = _subslices
static const struct gen_device_info gen_device_info_icl_8x8 = {
GEN11_FEATURES(2, 1, subslices(8), 8),
};
static const struct gen_device_info gen_device_info_icl_6x8 = {
GEN11_FEATURES(1, 1, subslices(6), 6),
};
static const struct gen_device_info gen_device_info_icl_4x8 = {
GEN11_FEATURES(1, 1, subslices(4), 6),
};
static const struct gen_device_info gen_device_info_icl_1x8 = {
GEN11_FEATURES(1, 1, subslices(1), 6),
};
>>
>> 1, 1, 1 ?
>>
>>> +};
>>> +
>>> bool
>>> gen_get_device_info(int devid, struct gen_device_info *devinfo)
>>> {
>>> @@ -757,10 +800,21 @@ gen_get_device_info(int devid, struct gen_device_info
>>> *devinfo)
>>> * Extra padding can be necessary depending how the thread IDs are
>>> * calculated for a particular shader stage.
>>> */
>>> - if (devinfo->gen >= 9) {
>>> +
>>> + switch(devinfo->gen) {
>>> + case 9:
>>> + case 10:
>>> devinfo->max_wm_threads = 64 /* threads-per-PSD */
>>> * devinfo->num_slices
>>> * 4; /* effective subslices per slice */
>>> + break;
>>> + case 11:
>>> + devinfo->max_wm_threads = 128 /* threads-per-PSD */
>>> + * devinfo->num_slices
>>> + * 8; /* subslices per slice */
>>> + break;
>>> + default:
>>> + break;
>>> }
>>>
>>> assert(devinfo->num_slices <= ARRAY_SIZE(devinfo->num_subslices));
>>> --
>>> 2.16.1
>>>
>>> _______________________________________________
>>> mesa-dev mailing list
>>> mesa-dev@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>> _______________________________________________
>> mesa-dev mailing list
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