On Wed, Feb 21, 2018 at 2:05 AM, Iago Toral <ito...@igalia.com> wrote:
> On Tue, 2018-02-20 at 21:15 -0800, Matt Turner wrote:
>> Gen11 does not support DF, Q, UQ types in hardware. As a result, we
>> have
>> to disable some GL extensions until they can be reimplemented.
>> ---
>> src/intel/common/gen_device_info.c | 3 +++
>> src/intel/common/gen_device_info.h | 1 +
>> src/mesa/drivers/dri/i965/intel_extensions.c | 9 +++++----
>> 3 files changed, 9 insertions(+), 4 deletions(-)
>>
>> diff --git a/src/intel/common/gen_device_info.c
>> b/src/intel/common/gen_device_info.c
>> index 8bf4b6b9bb0..465d4c783a1 100644
>> --- a/src/intel/common/gen_device_info.c
>> +++ b/src/intel/common/gen_device_info.c
>> @@ -138,6 +138,7 @@ static const struct gen_device_info
>> gen_device_info_snb_gt2 = {
>> .must_use_separate_stencil = true, \
>> .has_llc = true, \
>> .has_pln = true, \
>> + .has_64bit_types = true, \
>> .has_surface_tile_offset = true, \
>> .timestamp_frequency = 12500000
>>
>> @@ -322,6 +323,7 @@ static const struct gen_device_info
>> gen_device_info_hsw_gt3 = {
>> .has_llc = true, \
>> .has_sample_with_hiz = false, \
>> .has_pln = true, \
>> + .has_64bit_types = true, \
>> .supports_simd16_3src = true, \
>> .has_surface_tile_offset = true, \
>> .max_vs_threads = 504, \
>> @@ -756,6 +758,7 @@ static const struct gen_device_info
>> gen_device_info_cnl_5x8 = {
>> #define GEN11_FEATURES(_gt, _slices, _l3) \
>> GEN8_FEATURES, \
>> GEN11_HW_INFO, \
>> + .has_64bit_types = false, @@ -322,6 +323,7 @@ static
>> const struct gen_device_info gen_device_info_hsw_gt3 = {
>> \
>> .gt = _gt, .num_slices = _slices, .l3_banks = _l3
>
> This seems to only enable 64-bit types on snb_gt2 and hsw_gt3, what
> about bdw+ platforms? or ivybridge where we also support fp64?
Sorry, I should have sent the diff with more context. git diff's
context lines are useless, since we're modifying macros here:
GEN7_FEATURES, GEN8_FEATURES, and GEN11_FEATURES (which includes
GEN8_FEATURES).
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