Anuj Phogat <anuj.pho...@gmail.com> writes:
> On Wed, Feb 7, 2018 at 11:56 AM, Francisco Jerez <curroje...@riseup.net>
> wrote:
>
>> Anuj Phogat <anuj.pho...@gmail.com> writes:
>>
>> > Commit bit in the message descriptor (Bit 13) must be always set
>> > to true in CNL+ for memory fence messages. It also fixes a piglit
>> > GPU hang on cnl+ in simulation environment.
>> > Piglit test: arb_shader_image_load_store-shader-mem-barrier
>> > See HSD ES # 1404612949
>> >
>> > Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
>> > Cc: mesa-sta...@lists.freedesktop.org
>> > ---
>> > src/intel/compiler/brw_eu_emit.c | 4 +++-
>> > 1 file changed, 3 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/src/intel/compiler/brw_eu_emit.c
>> b/src/intel/compiler/brw_eu_emit.c
>> > index c25d8d6eda..1fb9aab51c 100644
>> > --- a/src/intel/compiler/brw_eu_emit.c
>> > +++ b/src/intel/compiler/brw_eu_emit.c
>> > @@ -3275,7 +3275,9 @@ brw_memory_fence(struct brw_codegen *p,
>> > struct brw_reg dst)
>> > {
>> > const struct gen_device_info *devinfo = p->devinfo;
>> > - const bool commit_enable = devinfo->gen == 7 && !devinfo->is_haswell;
>> > + const bool commit_enable =
>> > + devinfo->gen >= 10 || /* HSD ES # 1404612949 */
>> > + (devinfo->gen == 7 && !devinfo->is_haswell);
>>
>> A BSpec quote if you have one would be more informative here than the
>> HSD ES number, particularly if the reader is not on the Intel VPN. With
>> that change:
>>
> I tried but couldn't find a BSpec change. I'll try once more.
> Does your r-b still apply?
>Yes, it's not a big deal, patch is r-b either way. >> >> Reviewed-by: Francisco Jerez <curroje...@riseup.net> >> >> > struct brw_inst *insn; >> > >> > brw_push_insn_state(p); >> > -- >> > 2.13.6 >> > >> > _______________________________________________ >> > mesa-dev mailing list >> > mesa-dev@lists.freedesktop.org >> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev >>
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