FYI: I sent out a patch a few minutes ago to set the minimum version more like autotools does, but I'm fine with this landing first.
Reviewed-by: Dylan Baker <dy...@pnwbakers.com>
Quoting Marek Olšák (2018-02-02 11:07:57)
> Adding this:
>
> diff --git a/meson.build b/meson.build
> index 80ea60f..22eb702 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -991,12 +991,12 @@ endif
> _llvm = get_option('llvm')
> if _llvm == 'auto'
> dep_llvm = dependency(
> - 'llvm', version : '>= 3.9.0', modules : llvm_modules,
> + 'llvm', version : '>= 4.0.0', modules : llvm_modules,
> required : with_amd_vk or with_gallium_radeonsi or with_gallium_swr or
> with_gallium_opencl,
> )
> with_llvm = dep_llvm.found()
> elif _llvm == 'true'
> - dep_llvm = dependency('llvm', version : '>= 3.9.0', modules : llvm_modules)
> + dep_llvm = dependency('llvm', version : '>= 4.0.0', modules : llvm_modules)
> with_llvm = true
> else
> dep_llvm = []
> @@ -1019,7 +1019,7 @@ if with_llvm
> '-DMESA_LLVM_VERSION_PATCH=@0@'.format(_llvm_patch),
> ]
> elif with_amd_vk or with_gallium_radeonsi or with_gallium_swr
> - error('The following drivers requires LLVM: Radv, RadeonSI, SWR. One of
> these is enabled, but LLVM is disabled.')
> + error('The following drivers require LLVM: Radv, RadeonSI, SWR. One of
> these
> is enabled, but LLVM is disabled.')
> endif
>
> dep_glvnd = []
>
> Marek
>
> On Fri, Feb 2, 2018 at 8:02 PM, Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
> wrote:
>
> Also change meson.build?
>
> On Fri, Feb 2, 2018 at 7:34 PM, Marek Olšák <mar...@gmail.com> wrote:
> > From: Marek Olšák <marek.ol...@amd.com>
> >
> > Only these are supported:
> > - LLVM 4.0
> > - LLVM 5.0
> > - LLVM 6.0
> > - master (7.0)
> > ---
> > configure.ac | 4 +-
> > src/amd/common/ac_llvm_build.c | 187
> ++++++---------------
> > src/amd/common/ac_llvm_helper.cpp | 10 --
> > src/amd/common/ac_llvm_util.c | 39 +----
> > src/amd/common/ac_llvm_util.h | 14 +-
> > src/amd/common/ac_nir_to_llvm.c | 32 +---
> > src/amd/vulkan/radv_device.c | 4 -
> > src/gallium/drivers/radeonsi/si_compute.c | 3 +-
> > src/gallium/drivers/radeonsi/si_get.c | 13 +-
> > src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c | 3 +-
> > .../drivers/radeonsi/si_shader_tgsi_setup.c | 2 -
> > 11 files changed, 72 insertions(+), 239 deletions(-)
> >
> > diff --git a/configure.ac b/configure.ac
> > index a54b7cb..8ed606c 100644
> > --- a/configure.ac
> > +++ b/configure.ac
> > @@ -96,22 +96,22 @@ XDAMAGE_REQUIRED=1.1
> > XSHMFENCE_REQUIRED=1.1
> > XVMC_REQUIRED=1.0.6
> > PYTHON_MAKO_REQUIRED=0.8.0
> > LIBSENSORS_REQUIRED=4.0.0
> > ZLIB_REQUIRED=1.2.3
> >
> > dnl LLVM versions
> > LLVM_REQUIRED_GALLIUM=3.3.0
> > LLVM_REQUIRED_OPENCL=3.9.0
> > LLVM_REQUIRED_R600=3.9.0
> > -LLVM_REQUIRED_RADEONSI=3.9.0
> > -LLVM_REQUIRED_RADV=3.9.0
> > +LLVM_REQUIRED_RADEONSI=4.0.0
> > +LLVM_REQUIRED_RADV=4.0.0
> > LLVM_REQUIRED_SWR=3.9.0
> >
> > dnl Check for progs
> > AC_PROG_CPP
> > AC_PROG_CC
> > AC_PROG_CXX
> > dnl add this here, so the help for this environmnet variable is close
> to
> > dnl other CC/CXX flags related help
> > AC_ARG_VAR([CXX11_CXXFLAGS], [Compiler flag to enable C++11 support
> (only needed if not
> > enabled by default and different from
> -std=c++11)])
> > diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_
> build.c
> > index 6ede60a..3efcaa1 100644
> > --- a/src/amd/common/ac_llvm_build.c
> > +++ b/src/amd/common/ac_llvm_build.c
> > @@ -213,22 +213,21 @@ ac_to_float(struct ac_llvm_context *ctx,
> LLVMValueRef v)
> > return LLVMBuildBitCast(ctx->builder, v, ac_to_float_type(ctx,
> type), "");
> > }
> >
> >
> > LLVMValueRef
> > ac_build_intrinsic(struct ac_llvm_context *ctx, const char *name,
> > LLVMTypeRef return_type, LLVMValueRef *params,
> > unsigned param_count, unsigned attrib_mask)
> > {
> > LLVMValueRef function, call;
> > - bool set_callsite_attrs = HAVE_LLVM >= 0x0400 &&
> > - !(attrib_mask & AC_FUNC_ATTR_LEGACY);
> > + bool set_callsite_attrs = !(attrib_mask & AC_FUNC_ATTR_LEGACY);
> >
> > function = LLVMGetNamedFunction(ctx->module, name);
> > if (!function) {
> > LLVMTypeRef param_types[32], function_type;
> > unsigned i;
> >
> > assert(param_count <= 32);
> >
> > for (i = 0; i < param_count; ++i) {
> > assert(params[i]);
> > @@ -714,34 +713,20 @@ ac_prepare_cube_coords(struct ac_llvm_context
> *ctx,
> > LLVMValueRef
> > ac_build_fs_interp(struct ac_llvm_context *ctx,
> > LLVMValueRef llvm_chan,
> > LLVMValueRef attr_number,
> > LLVMValueRef params,
> > LLVMValueRef i,
> > LLVMValueRef j)
> > {
> > LLVMValueRef args[5];
> > LLVMValueRef p1;
> > -
> > - if (HAVE_LLVM < 0x0400) {
> > - LLVMValueRef ij[2];
> > - ij[0] = LLVMBuildBitCast(ctx->builder, i, ctx->i32, "");
> > - ij[1] = LLVMBuildBitCast(ctx->builder, j, ctx->i32, "");
> > -
> > - args[0] = llvm_chan;
> > - args[1] = attr_number;
> > - args[2] = params;
> > - args[3] = ac_build_gather_values(ctx, ij, 2);
> > - return ac_build_intrinsic(ctx, "llvm.SI.fs.interp",
> > - ctx->f32, args, 4,
> > - AC_FUNC_ATTR_READNONE);
> > - }
> >
> > args[0] = i;
> > args[1] = llvm_chan;
> > args[2] = attr_number;
> > args[3] = params;
> >
> > p1 = ac_build_intrinsic(ctx, "llvm.amdgcn.interp.p1",
> > ctx->f32, args, 4,
> AC_FUNC_ATTR_READNONE);
> >
> > args[0] = p1;
> > @@ -755,30 +740,20 @@ ac_build_fs_interp(struct ac_llvm_context *ctx,
> > }
> >
> > LLVMValueRef
> > ac_build_fs_interp_mov(struct ac_llvm_context *ctx,
> > LLVMValueRef parameter,
> > LLVMValueRef llvm_chan,
> > LLVMValueRef attr_number,
> > LLVMValueRef params)
> > {
> > LLVMValueRef args[4];
> > - if (HAVE_LLVM < 0x0400) {
> > - args[0] = llvm_chan;
> > - args[1] = attr_number;
> > - args[2] = params;
> > -
> > - return ac_build_intrinsic(ctx,
> > - "llvm.SI.fs.constant",
> > - ctx->f32, args, 3,
> > - AC_FUNC_ATTR_READNONE);
> > - }
> >
> > args[0] = parameter;
> > args[1] = llvm_chan;
> > args[2] = attr_number;
> > args[3] = params;
> >
> > return ac_build_intrinsic(ctx, "llvm.amdgcn.interp.mov",
> > ctx->f32, args, 4,
> AC_FUNC_ATTR_READNONE);
> > }
> >
> > @@ -1202,34 +1177,31 @@ ac_build_ddxy(struct ac_llvm_context *ctx,
> > result = LLVMBuildFSub(ctx->builder, trbl, tl, "");
> > return result;
> > }
> >
> > void
> > ac_build_sendmsg(struct ac_llvm_context *ctx,
> > uint32_t msg,
> > LLVMValueRef wave_id)
> > {
> > LLVMValueRef args[2];
> > - const char *intr_name = (HAVE_LLVM < 0x0400) ? "llvm.SI.sendmsg"
> : "llvm.amdgcn.s.sendmsg";
> > args[0] = LLVMConstInt(ctx->i32, msg, false);
> > args[1] = wave_id;
> > - ac_build_intrinsic(ctx, intr_name, ctx->voidt, args, 2, 0);
> > + ac_build_intrinsic(ctx, "llvm.amdgcn.s.sendmsg", ctx->voidt,
> args, 2, 0);
> > }
> >
> > LLVMValueRef
> > ac_build_imsb(struct ac_llvm_context *ctx,
> > LLVMValueRef arg,
> > LLVMTypeRef dst_type)
> > {
> > - const char *intr_name = (HAVE_LLVM < 0x0400) ?
> "llvm.AMDGPU.flbit.i32" :
> > -
> "llvm.amdgcn.sffbh.i32";
> > - LLVMValueRef msb = ac_build_intrinsic(ctx, intr_name,
> > + LLVMValueRef msb = ac_build_intrinsic(ctx,
> "llvm.amdgcn.sffbh.i32",
> > dst_type, &arg, 1,
> > AC_FUNC_ATTR_READNONE);
> >
> > /* The HW returns the last bit index from MSB, but NIR/TGSI
> wants
> > * the index from LSB. Invert it by doing "31 - msb". */
> > msb = LLVMBuildSub(ctx->builder, LLVMConstInt(ctx->i32, 31,
> false),
> > msb, "");
> >
> > LLVMValueRef all_ones = LLVMConstInt(ctx->i32, -1, true);
> > LLVMValueRef cond = LLVMBuildOr(ctx->builder,
> > @@ -1363,151 +1335,90 @@ void ac_build_export(struct ac_llvm_context
> *ctx, struct ac_export_args *a)
> > args[4] = LLVMConstInt(ctx->i32, a->compr, 0);
> > memcpy(args + 5, a->out, sizeof(a->out[0]) * 4);
> >
> > ac_build_intrinsic(ctx, "llvm.SI.export", ctx->voidt, args, 9,
> > AC_FUNC_ATTR_LEGACY);
> > }
> >
> > LLVMValueRef ac_build_image_opcode(struct ac_llvm_context *ctx,
> > struct ac_image_args *a)
> > {
> > - LLVMTypeRef dst_type;
> > LLVMValueRef args[11];
> > unsigned num_args = 0;
> > const char *name = NULL;
> > char intr_name[128], type[64];
> >
> > - if (HAVE_LLVM >= 0x0400) {
> > - bool sample = a->opcode == ac_image_sample ||
> > - a->opcode == ac_image_gather4 ||
> > - a->opcode == ac_image_get_lod;
> > -
> > - if (sample)
> > - args[num_args++] = ac_to_float(ctx, a->addr);
> > - else
> > - args[num_args++] = a->addr;
> > -
> > - args[num_args++] = a->resource;
> > - if (sample)
> > - args[num_args++] = a->sampler;
> > - args[num_args++] = LLVMConstInt(ctx->i32, a->dmask, 0);
> > - if (sample)
> > - args[num_args++] = LLVMConstInt(ctx->i1, a->
> unorm, 0);
> > - args[num_args++] = ctx->i1false; /* glc */
> > - args[num_args++] = ctx->i1false; /* slc */
> > - args[num_args++] = ctx->i1false; /* lwe */
> > - args[num_args++] = LLVMConstInt(ctx->i1, a->da, 0);
> > -
> > - switch (a->opcode) {
> > - case ac_image_sample:
> > - name = "llvm.amdgcn.image.sample";
> > - break;
> > - case ac_image_gather4:
> > - name = "llvm.amdgcn.image.gather4";
> > - break;
> > - case ac_image_load:
> > - name = "llvm.amdgcn.image.load";
> > - break;
> > - case ac_image_load_mip:
> > - name = "llvm.amdgcn.image.load.mip";
> > - break;
> > - case ac_image_get_lod:
> > - name = "llvm.amdgcn.image.getlod";
> > - break;
> > - case ac_image_get_resinfo:
> > - name = "llvm.amdgcn.image.getresinfo";
> > - break;
> > - default:
> > - unreachable("invalid image opcode");
> > - }
> > + bool sample = a->opcode == ac_image_sample ||
> > + a->opcode == ac_image_gather4 ||
> > + a->opcode == ac_image_get_lod;
> >
> > - ac_build_type_name_for_intr(LLVMTypeOf(args[0]), type,
> > - sizeof(type));
> > -
> > - snprintf(intr_name, sizeof(intr_name),
> "%s%s%s%s.v4f32.%s.v8i32",
> > - name,
> > - a->compare ? ".c" : "",
> > - a->bias ? ".b" :
> > - a->lod ? ".l" :
> > - a->deriv ? ".d" :
> > - a->level_zero ? ".lz" : "",
> > - a->offset ? ".o" : "",
> > - type);
> > -
> > - LLVMValueRef result =
> > - ac_build_intrinsic(ctx, intr_name,
> > - ctx->v4f32, args, num_args,
> > - AC_FUNC_ATTR_READNONE);
> > - if (!sample) {
> > - result = LLVMBuildBitCast(ctx->builder, result,
> > - ctx->v4i32, "");
> > - }
> > - return result;
> > - }
> > + if (sample)
> > + args[num_args++] = ac_to_float(ctx, a->addr);
> > + else
> > + args[num_args++] = a->addr;
> >
> > - args[num_args++] = a->addr;
> > args[num_args++] = a->resource;
> > -
> > - if (a->opcode == ac_image_load ||
> > - a->opcode == ac_image_load_mip ||
> > - a->opcode == ac_image_get_resinfo) {
> > - dst_type = ctx->v4i32;
> > - } else {
> > - dst_type = ctx->v4f32;
> > + if (sample)
> > args[num_args++] = a->sampler;
> > - }
> > -
> > args[num_args++] = LLVMConstInt(ctx->i32, a->dmask, 0);
> > - args[num_args++] = LLVMConstInt(ctx->i32, a->unorm, 0);
> > - args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
> > - args[num_args++] = LLVMConstInt(ctx->i32, a->da, 0);
> > - args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
> > - args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
> > - args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
> > - args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
> > + if (sample)
> > + args[num_args++] = LLVMConstInt(ctx->i1, a->unorm, 0);
> > + args[num_args++] = ctx->i1false; /* glc */
> > + args[num_args++] = ctx->i1false; /* slc */
> > + args[num_args++] = ctx->i1false; /* lwe */
> > + args[num_args++] = LLVMConstInt(ctx->i1, a->da, 0);
> >
> > switch (a->opcode) {
> > case ac_image_sample:
> > - name = "llvm.SI.image.sample";
> > + name = "llvm.amdgcn.image.sample";
> > break;
> > case ac_image_gather4:
> > - name = "llvm.SI.gather4";
> > + name = "llvm.amdgcn.image.gather4";
> > break;
> > case ac_image_load:
> > - name = "llvm.SI.image.load";
> > + name = "llvm.amdgcn.image.load";
> > break;
> > case ac_image_load_mip:
> > - name = "llvm.SI.image.load.mip";
> > + name = "llvm.amdgcn.image.load.mip";
> > break;
> > case ac_image_get_lod:
> > - name = "llvm.SI.getlod";
> > + name = "llvm.amdgcn.image.getlod";
> > break;
> > case ac_image_get_resinfo:
> > - name = "llvm.SI.getresinfo";
> > + name = "llvm.amdgcn.image.getresinfo";
> > break;
> > + default:
> > + unreachable("invalid image opcode");
> > }
> >
> > - ac_build_type_name_for_intr(LLVMTypeOf(a->addr), type, sizeof
> (type));
> > - snprintf(intr_name, sizeof(intr_name), "%s%s%s%s.%s",
> > + ac_build_type_name_for_intr(LLVMTypeOf(args[0]), type,
> > + sizeof(type));
> > +
> > + snprintf(intr_name, sizeof(intr_name),
> "%s%s%s%s.v4f32.%s.v8i32",
> > name,
> > a->compare ? ".c" : "",
> > a->bias ? ".b" :
> > a->lod ? ".l" :
> > a->deriv ? ".d" :
> > a->level_zero ? ".lz" : "",
> > a->offset ? ".o" : "",
> > type);
> >
> > - return ac_build_intrinsic(ctx, intr_name,
> > - dst_type, args, num_args,
> > - AC_FUNC_ATTR_READNONE |
> > - AC_FUNC_ATTR_LEGACY);
> > + LLVMValueRef result =
> > + ac_build_intrinsic(ctx, intr_name,
> > + ctx->v4f32, args, num_args,
> > + AC_FUNC_ATTR_READNONE);
> > + if (!sample) {
> > + result = LLVMBuildBitCast(ctx->builder, result,
> > + ctx->v4i32, "");
> > + }
> > + return result;
> > }
> >
> > LLVMValueRef ac_build_cvt_pkrtz_f16(struct ac_llvm_context *ctx,
> > LLVMValueRef args[2])
> > {
> > if (HAVE_LLVM >= 0x0500) {
> > LLVMTypeRef v2f16 =
> > LLVMVectorType(LLVMHalfTypeInContext(ctx->
> context), 2);
> > LLVMValueRef res =
> > ac_build_intrinsic(ctx, "llvm.amdgcn.cvt.pkrtz",
> > @@ -1731,33 +1642,29 @@ void ac_get_image_intr_name(const char
> *base_name,
> > LLVMTypeRef data_type,
> > LLVMTypeRef coords_type,
> > LLVMTypeRef rsrc_type,
> > char *out_name, unsigned out_len)
> > {
> > char coords_type_name[8];
> >
> > ac_build_type_name_for_intr(coords_type, coords_type_name,
> > sizeof(coords_type_name));
> >
> > - if (HAVE_LLVM <= 0x0309) {
> > - snprintf(out_name, out_len, "%s.%s", base_name,
> coords_type_name);
> > - } else {
> > - char data_type_name[8];
> > - char rsrc_type_name[8];
> > -
> > - ac_build_type_name_for_intr(data_type, data_type_name,
> > - sizeof(data_type_name));
> > - ac_build_type_name_for_intr(rsrc_type, rsrc_type_name,
> > - sizeof(rsrc_type_name));
> > - snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
> > - data_type_name, coords_type_name,
> rsrc_type_name);
> > - }
> > + char data_type_name[8];
> > + char rsrc_type_name[8];
> > +
> > + ac_build_type_name_for_intr(data_type, data_type_name,
> > + sizeof(data_type_name));
> > + ac_build_type_name_for_intr(rsrc_type, rsrc_type_name,
> > + sizeof(rsrc_type_name));
> > + snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
> > + data_type_name, coords_type_name, rsrc_type_name);
> > }
> >
> > #define AC_EXP_TARGET (HAVE_LLVM >= 0x0500 ? 0 : 3)
> > #define AC_EXP_OUT0 (HAVE_LLVM >= 0x0500 ? 2 : 5)
> >
> > enum ac_ir_type {
> > AC_IR_UNDEF,
> > AC_IR_CONST,
> > AC_IR_VALUE,
> > };
> > diff --git a/src/amd/common/ac_llvm_helper.cpp b/src/amd/common/ac_llvm_
> helper.cpp
> > index 793737c..1d2369b 100644
> > --- a/src/amd/common/ac_llvm_helper.cpp
> > +++ b/src/amd/common/ac_llvm_helper.cpp
> > @@ -58,54 +58,44 @@ void ac_add_attr_dereferenceable(LLVMValueRef val,
> uint64_t bytes)
> > bool ac_is_sgpr_param(LLVMValueRef arg)
> > {
> > llvm::Argument *A = llvm::unwrap<llvm::Argument>(arg);
> > llvm::AttributeList AS = A->getParent()->getAttributes();
> > unsigned ArgNo = A->getArgNo();
> > return AS.hasAttribute(ArgNo + 1, llvm::Attribute::InReg);
> > }
> >
> > LLVMValueRef ac_llvm_get_called_value(LLVMValueRef call)
> > {
> > -#if HAVE_LLVM >= 0x0309
> > return LLVMGetCalledValue(call);
> > -#else
> > - return llvm::wrap(llvm::CallSite(llvm::unwrap<llvm::Instruction>
> (call)).getCalledValue());
> > -#endif
> > }
> >
> > bool ac_llvm_is_function(LLVMValueRef v)
> > {
> > -#if HAVE_LLVM >= 0x0309
> > return LLVMGetValueKind(v) == LLVMFunctionValueKind;
> > -#else
> > - return llvm::isa<llvm::Function>(llvm::unwrap(v));
> > -#endif
> > }
> >
> > LLVMBuilderRef ac_create_builder(LLVMContextRef ctx,
> > enum ac_float_mode float_mode)
> > {
> > LLVMBuilderRef builder = LLVMCreateBuilderInContext(ctx);
> >
> > -#if HAVE_LLVM >= 0x0308
> > llvm::FastMathFlags flags;
> >
> > switch (float_mode) {
> > case AC_FLOAT_MODE_DEFAULT:
> > break;
> > case AC_FLOAT_MODE_NO_SIGNED_ZEROS_FP_MATH:
> > flags.setNoSignedZeros();
> > llvm::unwrap(builder)->setFastMathFlags(flags);
> > break;
> > case AC_FLOAT_MODE_UNSAFE_FP_MATH:
> > #if HAVE_LLVM >= 0x0600
> > flags.setFast();
> > #else
> > flags.setUnsafeAlgebra();
> > #endif
> > llvm::unwrap(builder)->setFastMathFlags(flags);
> > break;
> > }
> > -#endif
> >
> > return builder;
> > }
> > diff --git a/src/amd/common/ac_llvm_util.c
> b/src/amd/common/ac_llvm_util.
> c
> > index 5fd785a..b88c4e4 100644
> > --- a/src/amd/common/ac_llvm_util.c
> > +++ b/src/amd/common/ac_llvm_util.c
> > @@ -39,26 +39,25 @@ static void ac_init_llvm_target()
> > LLVMInitializeAMDGPUTarget();
> > LLVMInitializeAMDGPUTargetMC();
> > LLVMInitializeAMDGPUAsmPrinter();
> >
> > /* For inline assembly. */
> > LLVMInitializeAMDGPUAsmParser();
> >
> > /* Workaround for bug in llvm 4.0 that causes image intrinsics
> > * to disappear.
> > * https://reviews.llvm.org/D26348
> > + *
> > + * "mesa" is the prefix for error messages.
> > */
> > - if (HAVE_LLVM >= 0x0400) {
> > - /* "mesa" is the prefix for error messages */
> > - const char *argv[2] = { "mesa",
> "-simplifycfg-sink-common
> =false" };
> > - LLVMParseCommandLineOptions(2, argv, NULL);
> > - }
> > + const char *argv[2] = { "mesa", "-simplifycfg-sink-common=false"
> };
> > + LLVMParseCommandLineOptions(2, argv, NULL);
> > }
> >
> > static once_flag ac_init_llvm_target_once_flag = ONCE_FLAG_INIT;
> >
> > LLVMTargetRef ac_get_llvm_target(const char *triple)
> > {
> > LLVMTargetRef target = NULL;
> > char *err_message = NULL;
> >
> > call_once(&ac_init_llvm_target_once_flag, ac_init_llvm_target);
> > @@ -139,81 +138,51 @@ LLVMTargetMachineRef ac_create_target_machine(enum
> radeon_family family, enum ac
> > triple,
> > ac_get_llvm_processor_name(family),
> > features,
> > LLVMCodeGenLevelDefault,
> > LLVMRelocDefault,
> > LLVMCodeModelDefault);
> >
> > return tm;
> > }
> >
> > -
> > -#if HAVE_LLVM < 0x0400
> > -static LLVMAttribute ac_attr_to_llvm_attr(enum ac_func_attr attr)
> > -{
> > - switch (attr) {
> > - case AC_FUNC_ATTR_ALWAYSINLINE: return LLVMAlwaysInlineAttribute;
> > - case AC_FUNC_ATTR_INREG: return LLVMInRegAttribute;
> > - case AC_FUNC_ATTR_NOALIAS: return LLVMNoAliasAttribute;
> > - case AC_FUNC_ATTR_NOUNWIND: return LLVMNoUnwindAttribute;
> > - case AC_FUNC_ATTR_READNONE: return LLVMReadNoneAttribute;
> > - case AC_FUNC_ATTR_READONLY: return LLVMReadOnlyAttribute;
> > - default:
> > - fprintf(stderr, "Unhandled function attribute: %x\n", attr);
> > - return 0;
> > - }
> > -}
> > -
> > -#else
> > -
> > static const char *attr_to_str(enum ac_func_attr attr)
> > {
> > switch (attr) {
> > case AC_FUNC_ATTR_ALWAYSINLINE: return "alwaysinline";
> > case AC_FUNC_ATTR_INREG: return "inreg";
> > case AC_FUNC_ATTR_NOALIAS: return "noalias";
> > case AC_FUNC_ATTR_NOUNWIND: return "nounwind";
> > case AC_FUNC_ATTR_READNONE: return "readnone";
> > case AC_FUNC_ATTR_READONLY: return "readonly";
> > case AC_FUNC_ATTR_WRITEONLY: return "writeonly";
> > case AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY: return
> "inaccessiblememonly";
> > case AC_FUNC_ATTR_CONVERGENT: return "convergent";
> > default:
> > fprintf(stderr, "Unhandled function attribute: %x\n", attr);
> > return 0;
> > }
> > }
> >
> > -#endif
> > -
> > void
> > ac_add_function_attr(LLVMContextRef ctx, LLVMValueRef function,
> > int attr_idx, enum ac_func_attr attr)
> > {
> > -#if HAVE_LLVM < 0x0400
> > - LLVMAttribute llvm_attr = ac_attr_to_llvm_attr(attr);
> > - if (attr_idx == -1) {
> > - LLVMAddFunctionAttr(function, llvm_attr);
> > - } else {
> > - LLVMAddAttribute(LLVMGetParam(function, attr_idx - 1),
> llvm_attr);
> > - }
> > -#else
> > const char *attr_name = attr_to_str(attr);
> > unsigned kind_id = LLVMGetEnumAttributeKindForName(attr_name,
> > strlen
> (attr_name));
> > LLVMAttributeRef llvm_attr = LLVMCreateEnumAttribute(ctx, kind_id,
> 0);
> >
> > if (LLVMIsAFunction(function))
> > LLVMAddAttributeAtIndex(function, attr_idx, llvm_attr);
> > else
> > LLVMAddCallSiteAttribute(function, attr_idx, llvm_attr);
> > -#endif
> > }
> >
> > void ac_add_func_attributes(LLVMContextRef ctx, LLVMValueRef function,
> > unsigned attrib_mask)
> > {
> > attrib_mask |= AC_FUNC_ATTR_NOUNWIND;
> > attrib_mask &= ~AC_FUNC_ATTR_LEGACY;
> >
> > while (attrib_mask) {
> > enum ac_func_attr attr = 1u << u_bit_scan(&attrib_mask);
> > diff --git a/src/amd/common/ac_llvm_util.h
> b/src/amd/common/ac_llvm_util.
> h
> > index 29dc0c1..3cf385a 100644
> > --- a/src/amd/common/ac_llvm_util.h
> > +++ b/src/amd/common/ac_llvm_util.h
> > @@ -35,23 +35,23 @@
> > extern "C" {
> > #endif
> >
> > enum ac_func_attr {
> > AC_FUNC_ATTR_ALWAYSINLINE = (1 << 0),
> > AC_FUNC_ATTR_INREG = (1 << 2),
> > AC_FUNC_ATTR_NOALIAS = (1 << 3),
> > AC_FUNC_ATTR_NOUNWIND = (1 << 4),
> > AC_FUNC_ATTR_READNONE = (1 << 5),
> > AC_FUNC_ATTR_READONLY = (1 << 6),
> > - AC_FUNC_ATTR_WRITEONLY = HAVE_LLVM >= 0x0400 ? (1 << 7) : 0,
> > - AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY = HAVE_LLVM >= 0x0400 ? (1 <<
> 8) : 0,
> > - AC_FUNC_ATTR_CONVERGENT = HAVE_LLVM >= 0x0400 ? (1 << 9) : 0,
> > + AC_FUNC_ATTR_WRITEONLY = (1 << 7),
> > + AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY = (1 << 8),
> > + AC_FUNC_ATTR_CONVERGENT = (1 << 9),
> >
> > /* Legacy intrinsic that needs attributes on function
> declarations
> > * and they must match the internal LLVM definition exactly,
> otherwise
> > * intrinsic selection fails.
> > */
> > AC_FUNC_ATTR_LEGACY = (1u << 31),
> > };
> >
> > enum ac_target_machine_options {
> > AC_TM_SUPPORTS_SPILL = (1 << 0),
> > @@ -87,28 +87,26 @@ LLVMBuilderRef ac_create_builder(LLVMContextRef ctx,
> >
> > void
> > ac_llvm_add_target_dep_function_attr(LLVMValueRef F,
> > const char *name, int value);
> >
> > static inline unsigned
> > ac_get_load_intr_attribs(bool can_speculate)
> > {
> > /* READNONE means writes can't affect it, while READONLY means
> that
> > * writes can affect it. */
> > - return can_speculate && HAVE_LLVM >= 0x0400 ?
> > - AC_FUNC_ATTR_READNONE :
> > - AC_FUNC_ATTR_READONLY;
> > + return can_speculate ? AC_FUNC_ATTR_READNONE :
> > + AC_FUNC_ATTR_READONLY;
> > }
> >
> > static inline unsigned
> > ac_get_store_intr_attribs(bool writeonly_memory)
> > {
> > - return writeonly_memory && HAVE_LLVM >= 0x0400 ?
> > - AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY :
> > + return writeonly_memory ? AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY :
> > AC_FUNC_ATTR_WRITEONLY;
> > }
> >
> > #ifdef __cplusplus
> > }
> > #endif
> >
> > #endif /* AC_LLVM_UTIL_H */
> > diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_
> llvm.c
> > index 0f7d625..cfcd217 100644
> > --- a/src/amd/common/ac_nir_to_llvm.c
> > +++ b/src/amd/common/ac_nir_to_llvm.c
> > @@ -3628,32 +3628,24 @@ static LLVMValueRef visit_image_load(struct
> ac_nir_context *ctx,
> > dim == GLSL_SAMPLER_DIM_3D ||
> > dim == GLSL_SAMPLER_DIM_SUBPASS ||
> > dim == GLSL_SAMPLER_DIM_SUBPASS_MS;
> > LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->
> ac.i1false;
> > LLVMValueRef glc = ctx->ac.i1false;
> > LLVMValueRef slc = ctx->ac.i1false;
> >
> > params[0] = get_image_coords(ctx, instr);
> > params[1] = get_sampler_desc(ctx, instr->variables[0],
> AC_DESC_IMAGE, NULL, true, false);
> > params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /*
> dmask */
> > - if (HAVE_LLVM <= 0x0309) {
> > - params[3] = ctx->ac.i1false; /* r128 */
> > - params[4] = da;
> > - params[5] = glc;
> > - params[6] = slc;
> > - } else {
> > - LLVMValueRef lwe = ctx->ac.i1false;
> > - params[3] = glc;
> > - params[4] = slc;
> > - params[5] = lwe;
> > - params[6] = da;
> > - }
> > + params[3] = glc;
> > + params[4] = slc;
> > + params[5] = ctx->ac.i1false;
> > + params[6] = da;
> >
> > ac_get_image_intr_name("llvm.amdgcn.image.load",
> > ctx->ac.v4f32, /* vdata */
> > LLVMTypeOf(params[0]), /* coords
> *
> /
> > LLVMTypeOf(params[1]), /* rsrc */
> > intrinsic_name, sizeof
> (intrinsic_name));
> >
> > res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->
> ac.v4f32,
> > params, 7,
> AC_FUNC_ATTR_READONLY);
> > }
> > @@ -3687,32 +3679,24 @@ static void visit_image_store(struct
> ac_nir_context *ctx,
> > bool is_da = glsl_sampler_type_is_array(type) ||
> > dim == GLSL_SAMPLER_DIM_CUBE ||
> > dim == GLSL_SAMPLER_DIM_3D;
> > LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->
> ac.i1false;
> > LLVMValueRef slc = ctx->ac.i1false;
> >
> > params[0] = ac_to_float(&ctx->ac, get_src(ctx,
> instr->src
> [2]));
> > params[1] = get_image_coords(ctx, instr); /* coords */
> > params[2] = get_sampler_desc(ctx, instr->variables[0],
> AC_DESC_IMAGE, NULL, true, true);
> > params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /*
> dmask */
> > - if (HAVE_LLVM <= 0x0309) {
> > - params[4] = ctx->ac.i1false; /* r128 */
> > - params[5] = da;
> > - params[6] = glc;
> > - params[7] = slc;
> > - } else {
> > - LLVMValueRef lwe = ctx->ac.i1false;
> > - params[4] = glc;
> > - params[5] = slc;
> > - params[6] = lwe;
> > - params[7] = da;
> > - }
> > + params[4] = glc;
> > + params[5] = slc;
> > + params[6] = ctx->ac.i1false;
> > + params[7] = da;
> >
> > ac_get_image_intr_name("llvm.amdgcn.image.store",
> > LLVMTypeOf(params[0]), /* vdata
> */
> > LLVMTypeOf(params[1]), /* coords
> *
> /
> > LLVMTypeOf(params[2]), /* rsrc */
> > intrinsic_name, sizeof
> (intrinsic_name));
> >
> > ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->
> ac.voidt,
> > params, 8, 0);
> > }
> > diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> > index aea723c..9fda419 100644
> > --- a/src/amd/vulkan/radv_device.c
> > +++ b/src/amd/vulkan/radv_device.c
> > @@ -1106,25 +1106,21 @@ VkResult radv_CreateDevice(
> > device->pbb_allowed = device->physical_device->rad_
> info.chip_class >= GFX9 &&
> > (device->instance->perftest_flags &
> RADV_PERFTEST_BINNING);
> >
> > /* Disabled and not implemented for now. */
> > device->dfsm_allowed = device->pbb_allowed && false;
> >
> > #ifdef ANDROID
> > device->always_use_syncobj = device->physical_device->rad_
> info.has_syncobj_wait_for_submit;
> > #endif
> >
> > -#if HAVE_LLVM < 0x0400
> > - device->llvm_supports_spill = false;
> > -#else
> > device->llvm_supports_spill = true;
> > -#endif
> >
> > /* The maximum number of scratch waves. Scratch space isn't
> divided
> > * evenly between CUs. The number is only a function of the
> number of CUs.
> > * We can decrease the constant to decrease the scratch buffer
> size.
> > *
> > * sctx->scratch_waves must be >= the maximum posible size of
> > * 1 threadgroup, so that the hw doesn't hang from being unable
> > * to start any.
> > *
> > * The recommended value is 4 per CU at most. Higher numbers
> don't
> > diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/
> drivers/radeonsi/si_compute.c
> > index ac4fab3..91d6810 100644
> > --- a/src/gallium/drivers/radeonsi/si_compute.c
> > +++ b/src/gallium/drivers/radeonsi/si_compute.c
> > @@ -152,22 +152,21 @@ static void *si_create_compute_state(
> > struct si_context *sctx = (struct si_context *)ctx;
> > struct si_screen *sscreen = (struct si_screen *)ctx->screen;
> > struct si_compute *program = CALLOC_STRUCT(si_compute);
> >
> > pipe_reference_init(&program->reference, 1);
> > program->screen = (struct si_screen *)ctx->screen;
> > program->ir_type = cso->ir_type;
> > program->local_size = cso->req_local_mem;
> > program->private_size = cso->req_private_mem;
> > program->input_size = cso->req_input_mem;
> > - program->use_code_object_v2 = HAVE_LLVM >= 0x0400 &&
> > - cso->ir_type ==
> PIPE_SHADER_IR_NATIVE;
> > + program->use_code_object_v2 = cso->ir_type ==
> PIPE_SHADER_IR_NATIVE;
> >
> > if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
> > program->tokens = tgsi_dup_tokens(cso->prog);
> > if (!program->tokens) {
> > FREE(program);
> > return NULL;
> > }
> >
> > program->compiler_ctx_state.debug = sctx->debug;
> > program->compiler_ctx_state.is_debug_context = sctx->
> is_debug;
> > diff --git a/src/gallium/drivers/radeonsi/si_get.c
> b/src/gallium/drivers/
> radeonsi/si_get.c
> > index 36e6018..46d5eee 100644
> > --- a/src/gallium/drivers/radeonsi/si_get.c
> > +++ b/src/gallium/drivers/radeonsi/si_get.c
> > @@ -182,24 +182,22 @@ static int si_get_param(struct pipe_screen
> *pscreen, enum pipe_cap param)
> > case PIPE_CAP_MEMOBJ:
> > case PIPE_CAP_LOAD_CONSTBUF:
> > case PIPE_CAP_INT64:
> > case PIPE_CAP_INT64_DIVMOD:
> > case PIPE_CAP_TGSI_CLOCK:
> > case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
> > case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
> > case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
> > case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
> > case PIPE_CAP_TGSI_FS_FBFETCH:
> > - return 1;
> > -
> > case PIPE_CAP_TGSI_VOTE:
> > - return HAVE_LLVM >= 0x0400;
> > + return 1;
> >
> > case PIPE_CAP_TGSI_BALLOT:
> > return HAVE_LLVM >= 0x0500;
> >
> > case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
> > return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
> >
> > case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
> > return (sscreen->info.drm_major == 2 &&
> > sscreen->info.drm_minor >= 43) ||
> > @@ -737,28 +735,23 @@ static unsigned get_max_threads_per_block(struct
> si_screen *screen,
> > static int si_get_compute_param(struct pipe_screen *screen,
> > enum pipe_shader_ir ir_type,
> > enum pipe_compute_cap param,
> > void *ret)
> > {
> > struct si_screen *sscreen = (struct si_screen *)screen;
> >
> > //TODO: select these params by asic
> > switch (param) {
> > case PIPE_COMPUTE_CAP_IR_TARGET: {
> > - const char *gpu;
> > - const char *triple;
> > -
> > - if (HAVE_LLVM < 0x0400)
> > - triple = "amdgcn--";
> > - else
> > - triple = "amdgcn-mesa-mesa3d";
> > + const char *gpu, *triple;
> >
> > + triple = "amdgcn-mesa-mesa3d";
> > gpu = ac_get_llvm_processor_name(sscreen->info.family);
> > if (ret) {
> > sprintf(ret, "%s-%s", gpu, triple);
> > }
> > /* +2 for dash and terminating NIL byte */
> > return (strlen(triple) + strlen(gpu) + 2) *
> sizeof(char);
> > }
> > case PIPE_COMPUTE_CAP_GRID_DIMENSION:
> > if (ret) {
> > uint64_t *grid_dimension = ret;
> > diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c b/src/
> gallium/drivers/radeonsi/si_shader_tgsi_mem.c
> > index b5fad34..ec1de40 100644
> > --- a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
> > +++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
> > @@ -289,31 +289,30 @@ static void image_append_args(
> > LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
> > LLVMValueRef r128 = i1false;
> > LLVMValueRef da = tgsi_is_array_image(target) ? i1true :
> i1false;
> > LLVMValueRef glc =
> > force_glc ||
> > inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT |
> TGSI_MEMORY_VOLATILE) ?
> > i1true : i1false;
> > LLVMValueRef slc = i1false;
> > LLVMValueRef lwe = i1false;
> >
> > - if (atomic || (HAVE_LLVM <= 0x0309)) {
> > + if (atomic) {
> > emit_data->args[emit_data->arg_count++] = r128;
> > emit_data->args[emit_data->arg_count++] = da;
> > if (!atomic) {
> > emit_data->args[emit_data->arg_count++] = glc;
> > }
> > emit_data->args[emit_data->arg_count++] = slc;
> > return;
> > }
> >
> > - /* HAVE_LLVM >= 0x0400 */
> > emit_data->args[emit_data->arg_count++] = glc;
> > emit_data->args[emit_data->arg_count++] = slc;
> > emit_data->args[emit_data->arg_count++] = lwe;
> > emit_data->args[emit_data->arg_count++] = da;
> > }
> >
> > /**
> > * Append the resource and indexing arguments for buffer intrinsics.
> > *
> > * \param rsrc the v4i32 buffer resource
> > diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c b/src/
> gallium/drivers/radeonsi/si_shader_tgsi_setup.c
> > index f70e2bd..44294f2 100644
> > --- a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
> > +++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
> > @@ -1371,24 +1371,22 @@ void si_llvm_optimize_module(struct
> si_shader_context *ctx)
> > LLVMAddAlwaysInlinerPass(gallivm->passmgr);
> >
> > /* This pass should eliminate all the load and store
> instructions
> */
> > LLVMAddPromoteMemoryToRegisterPass(gallivm->passmgr);
> >
> > /* Add some optimization passes */
> > LLVMAddScalarReplAggregatesPass(gallivm->passmgr);
> > LLVMAddLICMPass(gallivm->passmgr);
> > LLVMAddAggressiveDCEPass(gallivm->passmgr);
> > LLVMAddCFGSimplificationPass(gallivm->passmgr);
> > -#if HAVE_LLVM >= 0x0400
> > /* This is recommended by the instruction combining pass. */
> > LLVMAddEarlyCSEMemSSAPass(gallivm->passmgr);
> > -#endif
> > LLVMAddInstructionCombiningPass(gallivm->passmgr);
> >
> > /* Run the pass */
> > LLVMRunPassManager(gallivm->passmgr, ctx->gallivm.module);
> >
> > LLVMDisposeBuilder(ctx->ac.builder);
> > LLVMDisposePassManager(gallivm->passmgr);
> > gallivm_dispose_target_library_info(target_library_info);
> > }
> >
> > --
> > 2.7.4
> >
> > _______________________________________________
> > mesa-dev mailing list
> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
>
signature.asc
Description: signature
_______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
