From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeon/r600_pipe_common.h | 4 ++++
src/gallium/drivers/radeon/r600_texture.c | 20 +++++++++-----------
2 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index d82e123..e2cd6c60 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -591,20 +591,24 @@ bool si_prepare_for_dma_blit(struct r600_common_context
*rctx,
struct r600_texture *rsrc,
unsigned src_level,
const struct pipe_box *src_box);
void si_texture_get_fmask_info(struct si_screen *sscreen,
struct r600_texture *rtex,
unsigned nr_samples,
struct r600_fmask_info *out);
void si_texture_get_cmask_info(struct si_screen *sscreen,
struct r600_texture *rtex,
struct r600_cmask_info *out);
+void si_eliminate_fast_color_clear(struct r600_common_context *rctx,
+ struct r600_texture *rtex);
+void si_texture_discard_cmask(struct si_screen *sscreen,
+ struct r600_texture *rtex);
bool si_init_flushed_depth_texture(struct pipe_context *ctx,
struct pipe_resource *texture,
struct r600_texture **staging);
void si_print_texture_info(struct si_screen *sscreen,
struct r600_texture *rtex, struct u_log_context
*log);
struct pipe_resource *si_texture_create(struct pipe_screen *screen,
const struct pipe_resource *templ);
bool vi_dcc_formats_compatible(enum pipe_format format1,
enum pipe_format format2);
bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index 36eff40..a0e9129 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -29,22 +29,20 @@
#include "util/u_memory.h"
#include "util/u_pack_color.h"
#include "util/u_resource.h"
#include "util/u_surface.h"
#include "util/os_time.h"
#include <errno.h>
#include <inttypes.h>
#include "state_tracker/drm_driver.h"
#include "amd/common/sid.h"
-static void r600_texture_discard_cmask(struct si_screen *sscreen,
- struct r600_texture *rtex);
static enum radeon_surf_mode
r600_choose_tiling(struct si_screen *sscreen,
const struct pipe_resource *templ);
bool si_prepare_for_dma_blit(struct r600_common_context *rctx,
struct r600_texture *rdst,
unsigned dst_level, unsigned dstx,
unsigned dsty, unsigned dstz,
struct r600_texture *rsrc,
@@ -83,21 +81,21 @@ bool si_prepare_for_dma_blit(struct r600_common_context
*rctx,
* SDMA. Otherwise, use the 3D path.
*/
if (rdst->cmask.size && rdst->dirty_level_mask & (1 << dst_level)) {
/* The CMASK clear is only enabled for the first level. */
assert(dst_level == 0);
if (!util_texrange_covers_whole_level(&rdst->resource.b.b,
dst_level,
dstx, dsty, dstz,
src_box->width,
src_box->height,
src_box->depth))
return false;
- r600_texture_discard_cmask(rctx->screen, rdst);
+ si_texture_discard_cmask(rctx->screen, rdst);
}
/* All requirements are met. Prepare textures for SDMA. */
if (rsrc->cmask.size && rsrc->dirty_level_mask & (1 << src_level))
rctx->b.flush_resource(&rctx->b, &rsrc->resource.b.b);
assert(!(rsrc->dirty_level_mask & (1 << src_level)));
assert(!(rdst->dirty_level_mask & (1 << dst_level)));
return true;
@@ -375,38 +373,38 @@ static void r600_surface_import_metadata(struct si_screen
*sscreen,
*array_mode = RADEON_SURF_MODE_2D;
else if (metadata->u.legacy.microtile == RADEON_LAYOUT_TILED)
*array_mode = RADEON_SURF_MODE_1D;
else
*array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
*is_scanout = metadata->u.legacy.scanout;
}
}
-static void r600_eliminate_fast_color_clear(struct r600_common_context *rctx,
- struct r600_texture *rtex)
+void si_eliminate_fast_color_clear(struct r600_common_context *rctx,
+ struct r600_texture *rtex)
{
struct si_screen *sscreen = rctx->screen;
struct pipe_context *ctx = &rctx->b;
if (ctx == sscreen->aux_context)
mtx_lock(&sscreen->aux_context_lock);
ctx->flush_resource(ctx, &rtex->resource.b.b);
ctx->flush(ctx, NULL, 0);
if (ctx == sscreen->aux_context)
mtx_unlock(&sscreen->aux_context_lock);
}
-static void r600_texture_discard_cmask(struct si_screen *sscreen,
- struct r600_texture *rtex)
+void si_texture_discard_cmask(struct si_screen *sscreen,
+ struct r600_texture *rtex)
{
if (!rtex->cmask.size)
return;
assert(rtex->resource.b.b.nr_samples <= 1);
/* Disable CMASK. */
memset(&rtex->cmask, 0, sizeof(rtex->cmask));
rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8;
rtex->dirty_level_mask = 0;
@@ -524,21 +522,21 @@ static void r600_reallocate_texture_inplace(struct
r600_common_context *rctx,
u_box_3d(0, 0, 0,
u_minify(templ.width0, i),
u_minify(templ.height0, i),
util_num_layers(&templ, i), &box);
rctx->dma_copy(&rctx->b, &new_tex->resource.b.b, i, 0,
0, 0,
&rtex->resource.b.b, i, &box);
}
}
if (new_bind_flag == PIPE_BIND_LINEAR) {
- r600_texture_discard_cmask(rctx->screen, rtex);
+ si_texture_discard_cmask(rctx->screen, rtex);
r600_texture_discard_dcc(rctx->screen, rtex);
}
/* Replace the structure fields of rtex. */
rtex->resource.b.b.bind = templ.bind;
pb_reference(&rtex->resource.buf, new_tex->resource.buf);
rtex->resource.gpu_address = new_tex->resource.gpu_address;
rtex->resource.vram_usage = new_tex->resource.vram_usage;
rtex->resource.gart_usage = new_tex->resource.gart_usage;
rtex->resource.bo_size = new_tex->resource.bo_size;
@@ -718,29 +716,29 @@ static boolean r600_texture_get_handle(struct
pipe_screen* screen,
if (si_texture_disable_dcc(rctx, rtex)) {
update_metadata = true;
/* si_texture_disable_dcc flushes the context */
flush = false;
}
}
if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) &&
(rtex->cmask.size || rtex->dcc_offset)) {
/* Eliminate fast clear (both CMASK and DCC) */
- r600_eliminate_fast_color_clear(rctx, rtex);
+ si_eliminate_fast_color_clear(rctx, rtex);
/* eliminate_fast_color_clear flushes the context */
flush = false;
/* Disable CMASK if flush_resource isn't going
* to be called.
*/
if (rtex->cmask.size)
- r600_texture_discard_cmask(sscreen, rtex);
+ si_texture_discard_cmask(sscreen, rtex);
}
/* Set metadata. */
if (!res->b.is_shared || update_metadata) {
r600_texture_init_metadata(sscreen, rtex, &metadata);
si_query_opaque_metadata(sscreen, rtex, &metadata);
sscreen->ws->buffer_set_metadata(res->buf, &metadata);
}
@@ -2263,21 +2261,21 @@ void vi_separate_dcc_try_enable(struct
r600_common_context *rctx,
tex->dcc_gather_statistics = true;
vi_separate_dcc_start_query(&rctx->b, tex);
}
if (!vi_should_enable_separate_dcc(tex))
return; /* stats show that DCC decompression is too expensive */
assert(tex->surface.num_dcc_levels);
assert(!tex->dcc_separate_buffer);
- r600_texture_discard_cmask(rctx->screen, tex);
+ si_texture_discard_cmask(rctx->screen, tex);
/* Get a DCC buffer. */
if (tex->last_dcc_separate_buffer) {
assert(tex->dcc_gather_statistics);
assert(!tex->dcc_separate_buffer);
tex->dcc_separate_buffer = tex->last_dcc_separate_buffer;
tex->last_dcc_separate_buffer = NULL;
} else {
tex->dcc_separate_buffer = (struct r600_resource*)
si_aligned_buffer_create(rctx->b.screen,
--
2.7.4
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