On 26 Jan. 2018 01:10, "Matthew Nicholls" <mnicho...@feralinteractive.com>
wrote:
Otherwise cache flushes could get conditionally disabled while still
clearing
the flush_bits, and thus flushes due to application pipeline barriers may
never
get executed.
I wonder would we better not predicating flushes. I added that as an extra
opt, but it might be the wrong move.
Dave.
Cc: mesa-sta...@lists.freedesktop.org
---
src/amd/vulkan/radv_meta_fast_clear.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/amd/vulkan/radv_meta_fast_clear.c
b/src/amd/vulkan/radv_meta_fast_clear.c
index fdeeaeedbf..f4353fd889 100644
--- a/src/amd/vulkan/radv_meta_fast_clear.c
+++ b/src/amd/vulkan/radv_meta_fast_clear.c
@@ -602,6 +602,8 @@ radv_emit_color_decompress(struct radv_cmd_buffer
*cmd_buffer,
}
if (!decompress_dcc && image->surface.dcc_size) {
+ si_emit_cache_flush(cmd_buffer);
+
radv_emit_set_predication_state_from_image(cmd_buffer,
image, true);
cmd_buffer->state.predicating = true;
}
--
2.13.6
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