According to LLVM, only pre-GFX9 targets do not flush denorms
for fmin/fmax.
All dEQP-VK.glsl.builtin.precision.* still pass.
Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
---
src/amd/common/ac_nir_to_llvm.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 8ae8650a7b..0120b3d87c 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1911,18 +1911,24 @@ static void visit_alu(struct ac_nir_context *ctx, const
nir_alu_instr *instr)
case nir_op_fmax:
result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
ac_to_float_type(&ctx->ac,
def_type), src[0], src[1]);
- if (instr->dest.dest.ssa.bit_size == 32)
+ if (ctx->ac.chip_class < GFX9 &&
+ instr->dest.dest.ssa.bit_size == 32) {
+ /* Only pre-GFX9 chips do not flush denorms. */
result = emit_intrin_1f_param(&ctx->ac,
"llvm.canonicalize",
ac_to_float_type(&ctx->ac, def_type),
result);
+ }
break;
case nir_op_fmin:
result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
ac_to_float_type(&ctx->ac,
def_type), src[0], src[1]);
- if (instr->dest.dest.ssa.bit_size == 32)
+ if (ctx->ac.chip_class < GFX9 &&
+ instr->dest.dest.ssa.bit_size == 32) {
+ /* Only pre-GFX9 chips do not flush denorms. */
result = emit_intrin_1f_param(&ctx->ac,
"llvm.canonicalize",
ac_to_float_type(&ctx->ac, def_type),
result);
+ }
break;
case nir_op_ffma:
result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
--
2.16.0
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