Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
for the series.
On Thu, Dec 21, 2017 at 5:53 PM, Samuel Pitoiset
<samuel.pitoi...@gmail.com> wrote:
> Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
> ---
> src/amd/common/ac_nir_to_llvm.c | 64 +++-------------------------
> src/amd/common/ac_shader_util.c | 72
> ++++++++++++++++++++++++++++++++
> src/amd/common/ac_shader_util.h | 6 +++
> src/gallium/drivers/radeonsi/si_shader.c | 61 +--------------------------
> 4 files changed, 84 insertions(+), 119 deletions(-)
>
> diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
> index 93624ee419..a90dd9f0a5 100644
> --- a/src/amd/common/ac_nir_to_llvm.c
> +++ b/src/amd/common/ac_nir_to_llvm.c
> @@ -6309,67 +6309,13 @@ si_export_mrt_color(struct nir_to_llvm_context *ctx,
> }
>
> static void
> -si_export_mrt_z(struct nir_to_llvm_context *ctx,
> - LLVMValueRef depth, LLVMValueRef stencil,
> - LLVMValueRef samplemask)
> +radv_export_mrt_z(struct nir_to_llvm_context *ctx,
> + LLVMValueRef depth, LLVMValueRef stencil,
> + LLVMValueRef samplemask)
> {
> struct ac_export_args args;
>
> - args.enabled_channels = 0;
> - args.valid_mask = 1;
> - args.done = 1;
> - args.target = V_008DFC_SQ_EXP_MRTZ;
> - args.compr = false;
> -
> - args.out[0] = LLVMGetUndef(ctx->ac.f32); /* R, depth */
> - args.out[1] = LLVMGetUndef(ctx->ac.f32); /* G, stencil test val[0:7],
> stencil op val[8:15] */
> - args.out[2] = LLVMGetUndef(ctx->ac.f32); /* B, sample mask */
> - args.out[3] = LLVMGetUndef(ctx->ac.f32); /* A, alpha to mask */
> -
> - unsigned format = ac_get_spi_shader_z_format(depth != NULL,
> - stencil != NULL,
> - samplemask != NULL);
> -
> - if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
> - assert(!depth);
> - args.compr = 1; /* COMPR flag */
> -
> - if (stencil) {
> - /* Stencil should be in X[23:16]. */
> - stencil = ac_to_integer(&ctx->ac, stencil);
> - stencil = LLVMBuildShl(ctx->builder, stencil,
> - LLVMConstInt(ctx->ac.i32, 16,
> 0), "");
> - args.out[0] = ac_to_float(&ctx->ac, stencil);
> - args.enabled_channels |= 0x3;
> - }
> - if (samplemask) {
> - /* SampleMask should be in Y[15:0]. */
> - args.out[1] = samplemask;
> - args.enabled_channels |= 0xc;
> - }
> - } else {
> - if (depth) {
> - args.out[0] = depth;
> - args.enabled_channels |= 0x1;
> - }
> -
> - if (stencil) {
> - args.out[1] = stencil;
> - args.enabled_channels |= 0x2;
> - }
> -
> - if (samplemask) {
> - args.out[2] = samplemask;
> - args.enabled_channels |= 0x4;
> - }
> - }
> -
> - /* SI (except OLAND and HAINAN) has a bug that it only looks
> - * at the X writemask component. */
> - if (ctx->options->chip_class == SI &&
> - ctx->options->family != CHIP_OLAND &&
> - ctx->options->family != CHIP_HAINAN)
> - args.enabled_channels |= 0x1;
> + ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
>
> ac_build_export(&ctx->ac, &args);
> }
> @@ -6417,7 +6363,7 @@ handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
> for (unsigned i = 0; i < index; i++)
> ac_build_export(&ctx->ac, &color_args[i]);
> if (depth || stencil || samplemask)
> - si_export_mrt_z(ctx, depth, stencil, samplemask);
> + radv_export_mrt_z(ctx, depth, stencil, samplemask);
> else if (!index) {
> si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true,
> &color_args[0]);
> ac_build_export(&ctx->ac, &color_args[0]);
> diff --git a/src/amd/common/ac_shader_util.c b/src/amd/common/ac_shader_util.c
> index 12f86dc677..531395f4f6 100644
> --- a/src/amd/common/ac_shader_util.c
> +++ b/src/amd/common/ac_shader_util.c
> @@ -22,7 +22,10 @@
> */
>
> #include <assert.h>
> +#include <stdlib.h>
> +#include <string.h>
>
> +#include "ac_nir_to_llvm.h"
> #include "ac_shader_util.h"
> #include "sid.h"
>
> @@ -105,3 +108,72 @@ ac_vgt_gs_mode(unsigned gs_max_vert_out, enum chip_class
> chip_class)
> S_028A40_GS_WRITE_OPTIMIZE(1) |
> S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0);
> }
> +
> +void
> +ac_export_mrt_z(struct ac_llvm_context *ctx, LLVMValueRef depth,
> + LLVMValueRef stencil, LLVMValueRef samplemask,
> + struct ac_export_args *args)
> +{
> + unsigned mask = 0;
> + unsigned format = ac_get_spi_shader_z_format(depth != NULL,
> + stencil != NULL,
> + samplemask != NULL);
> +
> + assert(depth || stencil || samplemask);
> +
> + memset(args, 0, sizeof(*args));
> +
> + args->valid_mask = 1; /* whether the EXEC mask is valid */
> + args->done = 1; /* DONE bit */
> +
> + /* Specify the target we are exporting */
> + args->target = V_008DFC_SQ_EXP_MRTZ;
> +
> + args->compr = 0; /* COMP flag */
> + args->out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
> + args->out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7],
> stencil op val[8:15] */
> + args->out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
> + args->out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
> +
> + if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
> + assert(!depth);
> + args->compr = 1; /* COMPR flag */
> +
> + if (stencil) {
> + /* Stencil should be in X[23:16]. */
> + stencil = ac_to_integer(ctx, stencil);
> + stencil = LLVMBuildShl(ctx->builder, stencil,
> + LLVMConstInt(ctx->i32, 16, 0),
> "");
> + args->out[0] = ac_to_float(ctx, stencil);
> + mask |= 0x3;
> + }
> + if (samplemask) {
> + /* SampleMask should be in Y[15:0]. */
> + args->out[1] = samplemask;
> + mask |= 0xc;
> + }
> + } else {
> + if (depth) {
> + args->out[0] = depth;
> + mask |= 0x1;
> + }
> + if (stencil) {
> + args->out[1] = stencil;
> + mask |= 0x2;
> + }
> + if (samplemask) {
> + args->out[2] = samplemask;
> + mask |= 0x4;
> + }
> + }
> +
> + /* SI (except OLAND and HAINAN) has a bug that it only looks
> + * at the X writemask component. */
> + if (ctx->chip_class == SI &&
> + ctx->family != CHIP_OLAND &&
> + ctx->family != CHIP_HAINAN)
> + mask |= 0x1;
> +
> + /* Specify which components to enable */
> + args->enabled_channels = mask;
> +}
> diff --git a/src/amd/common/ac_shader_util.h b/src/amd/common/ac_shader_util.h
> index 1bdf909e09..e4cf2bf576 100644
> --- a/src/amd/common/ac_shader_util.h
> +++ b/src/amd/common/ac_shader_util.h
> @@ -28,6 +28,7 @@
> #include <stdint.h>
>
> #include "amd_family.h"
> +#include "ac_llvm_build.h"
>
> unsigned
> ac_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
> @@ -39,4 +40,9 @@ ac_get_cb_shader_mask(unsigned spi_shader_col_format);
> uint32_t
> ac_vgt_gs_mode(unsigned gs_max_vert_out, enum chip_class chip_class);
>
> +void
> +ac_export_mrt_z(struct ac_llvm_context *ctx, LLVMValueRef depth,
> + LLVMValueRef stencil, LLVMValueRef samplemask,
> + struct ac_export_args *args);
> +
> #endif
> diff --git a/src/gallium/drivers/radeonsi/si_shader.c
> b/src/gallium/drivers/radeonsi/si_shader.c
> index 02e24f0c74..16b2ab9732 100644
> --- a/src/gallium/drivers/radeonsi/si_shader.c
> +++ b/src/gallium/drivers/radeonsi/si_shader.c
> @@ -3425,68 +3425,9 @@ static void si_export_mrt_z(struct
> lp_build_tgsi_context *bld_base,
> LLVMValueRef samplemask, struct si_ps_exports
> *exp)
> {
> struct si_shader_context *ctx = si_shader_context(bld_base);
> - struct lp_build_context *base = &bld_base->base;
> struct ac_export_args args;
> - unsigned mask = 0;
> - unsigned format = ac_get_spi_shader_z_format(depth != NULL,
> - stencil != NULL,
> - samplemask != NULL);
> -
> - assert(depth || stencil || samplemask);
> -
> - args.valid_mask = 1; /* whether the EXEC mask is valid */
> - args.done = 1; /* DONE bit */
> -
> - /* Specify the target we are exporting */
> - args.target = V_008DFC_SQ_EXP_MRTZ;
> -
> - args.compr = 0; /* COMP flag */
> - args.out[0] = base->undef; /* R, depth */
> - args.out[1] = base->undef; /* G, stencil test value[0:7], stencil op
> value[8:15] */
> - args.out[2] = base->undef; /* B, sample mask */
> - args.out[3] = base->undef; /* A, alpha to mask */
> -
> - if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
> - assert(!depth);
> - args.compr = 1; /* COMPR flag */
> -
> - if (stencil) {
> - /* Stencil should be in X[23:16]. */
> - stencil = ac_to_integer(&ctx->ac, stencil);
> - stencil = LLVMBuildShl(ctx->ac.builder, stencil,
> - LLVMConstInt(ctx->i32, 16, 0),
> "");
> - args.out[0] = ac_to_float(&ctx->ac, stencil);
> - mask |= 0x3;
> - }
> - if (samplemask) {
> - /* SampleMask should be in Y[15:0]. */
> - args.out[1] = samplemask;
> - mask |= 0xc;
> - }
> - } else {
> - if (depth) {
> - args.out[0] = depth;
> - mask |= 0x1;
> - }
> - if (stencil) {
> - args.out[1] = stencil;
> - mask |= 0x2;
> - }
> - if (samplemask) {
> - args.out[2] = samplemask;
> - mask |= 0x4;
> - }
> - }
> -
> - /* SI (except OLAND and HAINAN) has a bug that it only looks
> - * at the X writemask component. */
> - if (ctx->screen->info.chip_class == SI &&
> - ctx->screen->info.family != CHIP_OLAND &&
> - ctx->screen->info.family != CHIP_HAINAN)
> - mask |= 0x1;
>
> - /* Specify which components to enable */
> - args.enabled_channels = mask;
> + ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
>
> memcpy(&exp->args[exp->num++], &args, sizeof(args));
> }
> --
> 2.15.1
>
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