This reverts commit ff0f17da1446e7aa965e06c04a6ad5a55d95463d.
See the TODO.
Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
---
src/amd/vulkan/radv_image.c | 17 +++++++----------
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index efd17e4889..d2acfea86a 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -812,16 +812,13 @@ radv_image_alloc_htile(struct radv_image *image)
static inline bool
radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
{
- if (image->info.samples <= 1 &&
- image->info.width <= 512 && image->info.height <= 512) {
- /* Do not enable CMASK or DCC for small surfaces where the cost
- * of the eliminate pass can be higher than the benefit of fast
- * clear. RadeonSI does this, but the image threshold is
- * different.
- */
- return false;
- }
-
+ /* TODO: We should not enable CMASK or DCC for small surfaces because
+ * the cost of the eliminate pass can be higher than the benefit of
+ * fast clear. Note that radv does something bad when it's disabled,
+ * for example
dEQP-VK.pipeline.multisample_interpolation.sample_interpolate_at_single_sample.128_128_1.samples_1
+ * reports VM faults and hangs on Vega. This has to be fixed at some
+ * point.
+ */
return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
(image->exclusive || image->queue_family_mask == 1);
}
--
2.15.1
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