Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
On Fri, Dec 15, 2017 at 3:37 PM, Samuel Pitoiset
<samuel.pitoi...@gmail.com> wrote:
> Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
> ---
> src/amd/common/ac_shader_util.c | 35
> +++++++++++++++++++++++++
> src/amd/common/ac_shader_util.h | 3 +++
> src/amd/vulkan/radv_pipeline.c | 34 +-----------------------
> src/gallium/drivers/radeonsi/si_state_shaders.c | 34 +-----------------------
> 4 files changed, 40 insertions(+), 66 deletions(-)
>
> diff --git a/src/amd/common/ac_shader_util.c b/src/amd/common/ac_shader_util.c
> index 9d33a46559..ab8d3ed49b 100644
> --- a/src/amd/common/ac_shader_util.c
> +++ b/src/amd/common/ac_shader_util.c
> @@ -21,6 +21,8 @@
> * IN THE SOFTWARE.
> */
>
> +#include <assert.h>
> +
> #include "ac_shader_util.h"
> #include "sid.h"
>
> @@ -43,3 +45,36 @@ ac_get_spi_shader_z_format(bool writes_z, bool
> writes_stencil,
> return V_028710_SPI_SHADER_ZERO;
> }
> }
> +
> +unsigned
> +ac_get_cb_shader_mask(unsigned spi_shader_col_format)
> +{
> + unsigned i, cb_shader_mask = 0;
> +
> + for (i = 0; i < 8; i++) {
> + switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
> + case V_028714_SPI_SHADER_ZERO:
> + break;
> + case V_028714_SPI_SHADER_32_R:
> + cb_shader_mask |= 0x1 << (i * 4);
> + break;
> + case V_028714_SPI_SHADER_32_GR:
> + cb_shader_mask |= 0x3 << (i * 4);
> + break;
> + case V_028714_SPI_SHADER_32_AR:
> + cb_shader_mask |= 0x9 << (i * 4);
> + break;
> + case V_028714_SPI_SHADER_FP16_ABGR:
> + case V_028714_SPI_SHADER_UNORM16_ABGR:
> + case V_028714_SPI_SHADER_SNORM16_ABGR:
> + case V_028714_SPI_SHADER_UINT16_ABGR:
> + case V_028714_SPI_SHADER_SINT16_ABGR:
> + case V_028714_SPI_SHADER_32_ABGR:
> + cb_shader_mask |= 0xf << (i * 4);
> + break;
> + default:
> + assert(0);
> + }
> + }
> + return cb_shader_mask;
> +}
> diff --git a/src/amd/common/ac_shader_util.h b/src/amd/common/ac_shader_util.h
> index 1f971e76f1..d3804b8fb1 100644
> --- a/src/amd/common/ac_shader_util.h
> +++ b/src/amd/common/ac_shader_util.h
> @@ -30,4 +30,7 @@ unsigned
> ac_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
> bool writes_samplemask);
>
> +unsigned
> +ac_get_cb_shader_mask(unsigned spi_shader_col_format);
> +
> #endif
> diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
> index 1ada69d92f..1086f70d05 100644
> --- a/src/amd/vulkan/radv_pipeline.c
> +++ b/src/amd/vulkan/radv_pipeline.c
> @@ -416,38 +416,6 @@ static unsigned si_choose_spi_color_format(VkFormat
> vk_format,
> return normal;
> }
>
> -static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
> -{
> - unsigned i, cb_shader_mask = 0;
> -
> - for (i = 0; i < 8; i++) {
> - switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
> - case V_028714_SPI_SHADER_ZERO:
> - break;
> - case V_028714_SPI_SHADER_32_R:
> - cb_shader_mask |= 0x1 << (i * 4);
> - break;
> - case V_028714_SPI_SHADER_32_GR:
> - cb_shader_mask |= 0x3 << (i * 4);
> - break;
> - case V_028714_SPI_SHADER_32_AR:
> - cb_shader_mask |= 0x9 << (i * 4);
> - break;
> - case V_028714_SPI_SHADER_FP16_ABGR:
> - case V_028714_SPI_SHADER_UNORM16_ABGR:
> - case V_028714_SPI_SHADER_SNORM16_ABGR:
> - case V_028714_SPI_SHADER_UINT16_ABGR:
> - case V_028714_SPI_SHADER_SINT16_ABGR:
> - case V_028714_SPI_SHADER_32_ABGR:
> - cb_shader_mask |= 0xf << (i * 4);
> - break;
> - default:
> - assert(0);
> - }
> - }
> - return cb_shader_mask;
> -}
> -
> static void
> radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
> const VkGraphicsPipelineCreateInfo
> *pCreateInfo,
> @@ -477,7 +445,7 @@ radv_pipeline_compute_spi_color_formats(struct
> radv_pipeline *pipeline,
> col_format |= cf << (4 * i);
> }
>
> - blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
> + blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
>
> if (blend_mrt0_is_dual_src)
> col_format |= (col_format & 0xf) << 4;
> diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c
> b/src/gallium/drivers/radeonsi/si_state_shaders.c
> index 25854a1fde..d33008cdda 100644
> --- a/src/gallium/drivers/radeonsi/si_state_shaders.c
> +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
> @@ -981,38 +981,6 @@ static unsigned si_get_spi_shader_col_format(struct
> si_shader *shader)
> return value;
> }
>
> -static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
> -{
> - unsigned i, cb_shader_mask = 0;
> -
> - for (i = 0; i < 8; i++) {
> - switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
> - case V_028714_SPI_SHADER_ZERO:
> - break;
> - case V_028714_SPI_SHADER_32_R:
> - cb_shader_mask |= 0x1 << (i * 4);
> - break;
> - case V_028714_SPI_SHADER_32_GR:
> - cb_shader_mask |= 0x3 << (i * 4);
> - break;
> - case V_028714_SPI_SHADER_32_AR:
> - cb_shader_mask |= 0x9 << (i * 4);
> - break;
> - case V_028714_SPI_SHADER_FP16_ABGR:
> - case V_028714_SPI_SHADER_UNORM16_ABGR:
> - case V_028714_SPI_SHADER_SNORM16_ABGR:
> - case V_028714_SPI_SHADER_UINT16_ABGR:
> - case V_028714_SPI_SHADER_SINT16_ABGR:
> - case V_028714_SPI_SHADER_32_ABGR:
> - cb_shader_mask |= 0xf << (i * 4);
> - break;
> - default:
> - assert(0);
> - }
> - }
> - return cb_shader_mask;
> -}
> -
> static void si_shader_ps(struct si_shader *shader)
> {
> struct tgsi_shader_info *info = &shader->selector->info;
> @@ -1095,7 +1063,7 @@ static void si_shader_ps(struct si_shader *shader)
> spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
>
> spi_shader_col_format = si_get_spi_shader_col_format(shader);
> - cb_shader_mask = si_get_cb_shader_mask(spi_shader_col_format);
> + cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
>
> /* Ensure that some export memory is always allocated, for two
> reasons:
> *
> --
> 2.15.1
>
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