[Mesa-dev] [PATCH v2 18/20] radeonsi: add si_load_tess_level() helper

[Timothy Arceri]

This will be shared by the tgsi and nir backends.

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
---
 src/gallium/drivers/radeonsi/si_shader.c | 31 ++++++++++++++++++-------------
 1 file changed, 18 insertions(+), 13 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 7f874d06db6..17e55d7fc82 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1914,20 +1914,36 @@ static LLVMValueRef si_load_tess_coord(struct 
ac_shader_abi *abi,
 
        /* For triangles, the vector should be (u, v, 1-u-v). */
        if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] 
==
            PIPE_PRIM_TRIANGLES)
                coord[2] = lp_build_sub(bld, ctx->ac.f32_1,
                                        lp_build_add(bld, coord[0], coord[1]));
 
        return lp_build_gather_values(&ctx->gallivm, coord, 4);
 }
 
+static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi, int param)
+{
+       struct si_shader_context *ctx = si_shader_context_from_abi(abi);
+       LLVMValueRef buffer, base, addr;
+
+       buffer = desc_from_addr_base64k(ctx, 
ctx->param_tcs_offchip_addr_base64k);
+
+       base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
+       addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
+                                         LLVMConstInt(ctx->i32, param, 0));
+
+       return buffer_load(&ctx->bld_base, ctx->f32,
+                          ~0, buffer, base, addr, true);
+
+}
+
 void si_load_system_value(struct si_shader_context *ctx,
                          unsigned index,
                          const struct tgsi_full_declaration *decl)
 {
        LLVMValueRef value = 0;
 
        assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
 
        switch (decl->Semantic.Name) {
        case TGSI_SEMANTIC_INSTANCEID:
@@ -2031,34 +2047,23 @@ void si_load_system_value(struct si_shader_context *ctx,
        case TGSI_SEMANTIC_VERTICESIN:
                if (ctx->type == PIPE_SHADER_TESS_CTRL)
                        value = unpack_param(ctx, 
ctx->param_tcs_out_lds_layout, 26, 6);
                else if (ctx->type == PIPE_SHADER_TESS_EVAL)
                        value = get_num_tcs_out_vertices(ctx);
                else
                        assert(!"invalid shader stage for 
TGSI_SEMANTIC_VERTICESIN");
                break;
 
        case TGSI_SEMANTIC_TESSINNER:
-       case TGSI_SEMANTIC_TESSOUTER:
-       {
-               LLVMValueRef buffer, base, addr;
+       case TGSI_SEMANTIC_TESSOUTER: {
                int param = 
si_shader_io_get_unique_index_patch(decl->Semantic.Name, 0);
-
-               buffer = desc_from_addr_base64k(ctx, 
ctx->param_tcs_offchip_addr_base64k);
-
-               base = LLVMGetParam(ctx->main_fn, 
ctx->param_tcs_offchip_offset);
-               addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), 
NULL,
-                                         LLVMConstInt(ctx->i32, param, 0));
-
-               value = buffer_load(&ctx->bld_base, ctx->f32,
-                                   ~0, buffer, base, addr, true);
-
+               value = si_load_tess_level(&ctx->abi, param);
                break;
        }
 
        case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
        case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
        {
                LLVMValueRef buf, slot, val[4];
                int i, offset;
 
                slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 
0);
-- 
2.14.3

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