From: Jordan Justen <jordan.l.jus...@intel.com>
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>
---
src/mesa/drivers/dri/i965/brw_link.cpp | 9 ++-------
src/mesa/drivers/dri/i965/brw_program.c | 12 ++++++++++++
src/mesa/drivers/dri/i965/brw_program.h | 3 +++
3 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp
b/src/mesa/drivers/dri/i965/brw_link.cpp
index d18521e792d..6ac3a79a41e 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -295,27 +295,22 @@ brw_link_shader(struct gl_context *ctx, struct
gl_shader_program *shProg)
continue;
struct gl_program *prog = shader->Program;
brw_shader_gather_info(prog->nir, prog);
NIR_PASS_V(prog->nir, nir_lower_samplers, shProg);
NIR_PASS_V(prog->nir, nir_lower_atomics, shProg);
NIR_PASS_V(prog->nir, nir_lower_atomics_to_ssbo,
prog->nir->info.num_abos);
- if (brw->ctx.Cache) {
- struct blob writer;
- blob_init(&writer);
- nir_serialize(&writer, prog->nir);
- prog->driver_cache_blob = ralloc_size(NULL, writer.size);
- memcpy(prog->driver_cache_blob, writer.data, writer.size);
- prog->driver_cache_blob_size = writer.size;
+ if (ctx->Cache) {
+ brw_program_serialize_nir(ctx, prog, (gl_shader_stage)stage);
}
infos[stage] = &prog->nir->info;
update_xfb_info(prog->sh.LinkedTransformFeedback, infos[stage]);
/* Make a pass over the IR to add state references for any built-in
* uniforms that are used. This has to be done now (during linking).
* Code generation doesn't happen until the first time this shader is
* used for rendering. Waiting until then to generate the parameters is
diff --git a/src/mesa/drivers/dri/i965/brw_program.c
b/src/mesa/drivers/dri/i965/brw_program.c
index 30cc14e88a2..c8513c947da 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -780,20 +780,32 @@ brw_assign_common_binding_table_offsets(const struct
gen_device_info *devinfo,
stage_prog_data->binding_table.plane_start[2] = next_binding_table_offset;
next_binding_table_offset += num_textures;
/* prog_data->base.binding_table.size will be set by brw_mark_surface_used.
*/
assert(next_binding_table_offset <= BRW_MAX_SURFACES);
return next_binding_table_offset;
}
+void
+brw_program_serialize_nir(struct gl_context *ctx, struct gl_program *prog,
+ gl_shader_stage stage)
+{
+ struct blob writer;
+ blob_init(&writer);
+ nir_serialize(&writer, prog->nir);
+ prog->driver_cache_blob = ralloc_size(NULL, writer.size);
+ memcpy(prog->driver_cache_blob, writer.data, writer.size);
+ prog->driver_cache_blob_size = writer.size;
+}
+
void
brw_program_deserialize_nir(struct gl_context *ctx, struct gl_program *prog,
gl_shader_stage stage)
{
if (!prog->nir) {
assert(prog->driver_cache_blob && prog->driver_cache_blob_size > 0);
const struct nir_shader_compiler_options *options =
ctx->Const.ShaderCompilerOptions[stage].NirOptions;
struct blob_reader reader;
blob_reader_init(&reader, prog->driver_cache_blob,
diff --git a/src/mesa/drivers/dri/i965/brw_program.h
b/src/mesa/drivers/dri/i965/brw_program.h
index bd9b4ad168a..a5e41522841 100644
--- a/src/mesa/drivers/dri/i965/brw_program.h
+++ b/src/mesa/drivers/dri/i965/brw_program.h
@@ -75,20 +75,23 @@ bool brw_debug_recompile_sampler_key(struct brw_context
*brw,
const struct brw_sampler_prog_key_data
*old_key,
const struct brw_sampler_prog_key_data
*key);
uint32_t
brw_assign_common_binding_table_offsets(const struct gen_device_info *devinfo,
const struct gl_program *prog,
struct brw_stage_prog_data
*stage_prog_data,
uint32_t next_binding_table_offset);
void
+brw_program_serialize_nir(struct gl_context *ctx, struct gl_program *prog,
+ gl_shader_stage stage);
+void
brw_program_deserialize_nir(struct gl_context *ctx, struct gl_program *prog,
gl_shader_stage stage);
void
brw_stage_prog_data_free(const void *prog_data);
void
brw_dump_arb_asm(const char *stage, struct gl_program *prog);
bool brw_vs_precompile(struct gl_context *ctx, struct gl_program *prog);
--
2.14.3
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