Hello list,
The candidate for the Mesa 17.2.6 is now available. Currently we have:
- 51 queued
- 5 nominated (outstanding)
- and 13 rejected patches
In the current queue we have:
In Mesa Core we have included a correction to keep a program alive when
re-linking and prevent an use-after-free.
The GLSL compiler has received several fixes, including one to prevent
a SIGSEV when calling an undeclared subroutine in certain conditions
and another to mark the xfb buffers as active only if a variable uses
them.
The SPIR-V compiler has corrected a couple of issues involving the
usage of separate images and texture/samplers.
The Intel drivers include many new fixes, specially for i965. Several
are focused on improving SIMD32 and little-core. It also includes a fix
for a GPU hang which was detected while playing HW accelerated video
with mpv.
The AMD drivers have also received some care. radv has seen plugged 2
memory leaks while r600 has gotten a fix through reversing the tess
factor components for isolines.
The swr driver has corrected two performance regressions, one for the
avx512 platforms and the other for the avx/avx2 platforms.
In the ddebug gallium driver we have a fix for an use-after-free.
On the EGL side, the Wayland platform of the the DRI2 drivers has
received a fix to prevent crashing in ancient systems.
GLX has also received corrections to prevent a couple of errors when
creating and binding a context in DRI3 and DRISW, respectively.
From build and integration point of view, we have added some few more
fixes, including one to allow building libglvnd when EGL is present but
not GLX, another to enable building targets which don't need X11, such
as omx and va, when XCB is not present, and another one to be able to
specify the prefix installation for the OpenCL icd file.
Take a look at section "Mesa stable queue" for more information.
Testing reports/general approval
--------------------------------
Any testing reports (or general approval of the state of the branch)
will be greatly appreciated.
The plan is to have 17.2.6 next Saturday (26th of November), around or
shortly after 23:00 GMT.
If you have any questions or suggestions - be that about the current
patch queue or otherwise, please go ahead.
Trivial merge conflicts
-----------------------
commit dfa57d01e4ffc3707da192c17488330773f9a6c9
Author: Kenneth Graunke <kenn...@whitecape.org>
i965: properly initialize brw->cs.base.stage to MESA_SHADER_COMPUTE
(cherry picked from commit a16dc04ad51c32e5c7d136e4dd6273d983385d3f)
commit 82876e24c45f01e5209b7f8c0ab3430c54b6db28
Author: Anuj Phogat <anuj.pho...@gmail.com>
i965/gen8+: Fix the number of dwords programmed in MI_FLUSH_DW
(cherry picked from commit 1dc45d75bb3ff3085f7356b8ec658111529ff76d)
commit f288607eb76c8ab2afef2bb01405e5b7331e3dc2
Author: Kenneth Graunke <kenn...@whitecape.org>
i965: Implement another VF cache invalidate workaround on Gen8+.
(cherry picked from commit 8d48671492412e04c18651a779cabacf30ed0afe)
Squashed with:
i965: Revert Gen8 aspect of VF PIPE_CONTROL workaround.
(cherry picked from commit a01ba366e01b7d1cdfa6b0e6647536b10c0667ef)
Cheers,
Andres
Mesa stable queue
-----------------
Nominated (5)
=============
Gert Wollny (1):
1d076aafbc0 r600: Emit EOP for more CF instruction types
Juan A. Suarez Romero (1):
d5a641106ba glsl: add varying resources for arrays of complex types
Eduardo Lima Mitev (3):
4c62a270a99 glsl_parser_extra: Add utility to copy symbols between symbol
tables
f5fe99ac85e glsl: Use the utility function to copy symbols between symbol
tables
f9de7f55969 glsl/linker: Check that re-declared, inter-shader built-in
blocks match
Queued (51)
===========
Adam Jackson (2):
glx/drisw: Fix glXMakeCurrent(dpy, None, ctx)
glx/dri3: Fix passing renderType into glXCreateContext
Alex Smith (2):
spirv: Use correct type for sampled images
nir/spirv: tg4 requires a sampler
Andres Gomez (13):
docs: add sha256 checksums for 17.2.5
cherry-ignore: intel/fs: Use a pure vertical stride for large register
strides
cherry-ignore: intel/nir: Use the correct indirect lowering masks in
link_shaders
cherry-ignore: intel/fs: Use the original destination region for int MUL
lowering
cherry-ignore: intel/fs: refactors
cherry-ignore: r600/shader: reserve first register of vertex shader.
cherry-ignore: anv/cmd_buffer: Advance the address when initializing
clear colors
cherry-ignore: anv/cmd_buffer: Take bo_offset into account in fast clear
state addresses
cherry-ignore: i965: Mark BOs as external when we export their handle
cherry-ignore: added 17.3 nominations.
cherry-ignore: glsl: Fix typo fragement -> fragment
cherry-ignore: egl: pass the dri2_dpy to the $plat_teardown functions
cherry-ignore: Revert "intel/fs: Use a pure vertical stride for large
register strides"
Anuj Phogat (2):
i965: Program DWord Length in MI_FLUSH_DW
Squashed with
i965: Remove DWord length from MI_FLUSH_DW definition
i965/gen8+: Fix the number of dwords programmed in MI_FLUSH_DW
Bas Nieuwenhuizen (2):
radv: Free syncobj with multiple imports.
radv: Free temporary syncobj after waiting on it.
Dave Airlie (1):
r600: fix isoline tess factor component swapping.
Derek Foreman (1):
egl/wayland: Add a fallback when fourcc query isn't supported
Squashed with
egl: fix var type
Dylan Baker (1):
autotools: Set C++ visibility flags on Intel
Emil Velikov (3):
targets/opencl: don't hardcode the icd file install to /etc/...
configure.ac: loosen --enable-glvnd check to honour egl
configure.ac: require xcb* for the omx/va/... when using x11 platform
George Barrett (1):
glsl: Catch subscripted calls to undeclared subroutines
Jason Ekstrand (9):
intel/fs: Use ANY/ALL32 predicates in SIMD32
intel/fs: Use an explicit D type for vote any/all/eq intrinsics
intel/fs: Use a pair of 1-wide MOVs instead of SEL for any/all
intel/eu/reg: Add a subscript() helper
intel/fs: Fix MOV_INDIRECT for 64-bit values on little-core
intel/fs: Fix integer multiplication lowering for src/dst hazards
intel/fs: Mark 64-bit values as being contiguous
intel/fs: Rework zero-length URB write handling
i965: Add stencil buffers to cache set regardless of stencil texturing
Kenneth Graunke (5):
i965: properly initialize brw->cs.base.stage to MESA_SHADER_COMPUTE
i965: Make L3 configuration atom listen for TCS/TES program updates.
intel/tools: Fix detection of enabled shader stages.
i965: Implement another VF cache invalidate workaround on Gen8+.
Squashed with
i965: Revert Gen8 aspect of VF PIPE_CONTROL workaround.
i965: Upload invariant state once at the start of the batch on Gen4-5.
Matt Turner (2):
i965/fs: Fix extract_i8/u8 to a 64-bit destination
i965/fs: Split all 32->64-bit MOVs on CHV, BXT, GLK
Neil Roberts (1):
glsl: Transform fb buffers are only active if a variable uses them
Nicolai Hähnle (1):
ddebug: fix use-after-free of streamout targets
Tim Rowley (2):
swr/rast: Use gather instruction for i32gather_ps on simd16/avx512
swr/rast: Faster emulated simd16 permute
Timothy Arceri (3):
glsl: drop cache_fallback
glsl: use the correct parent when allocating program data members
mesa: rework how we free gl_shader_program_data
Rejected (13)
=============
Dave Airlie (1):
50330d7115f r600/shader: reserve first register of vertex shader.
Reason: Commit addressed earlier commit ea1b97714d9b which did not land
in branch.
Jason Ekstrand (12):
e8c9e65185d intel/fs: Use a pure vertical stride for large register
strides
Reason: Commit is not really needed after 6ac2d169019.
7364f080f9a intel/nir: Add a helper for getting the NoIndirect mask
3e63cf893f0 intel/nir: Break the linking code into a helper in brw_nir.c
951a5dc4cc2 intel/nir: Use the correct indirect lowering masks in
link_shaders
Reason: These 3 commits addressed earlier commit 379b24a40d3 which did
not land in branch.
18fde36ced4 intel/fs: Use the original destination region for int MUL
lowering
Reason: Commit resulted in a CTS regression being addressed at
https://bugs.freedesktop.org/show_bug.cgi?id=103626 .
fcd4adb9d08 intel/fs: Pass builders instead of blocks into emit_[un]zip
0d905597fe2 intel/fs: Be more explicit about our placement of [un]zip
6c00240bc65 intel/fs: Don't stomp f0.1 in SIMD16 ballot
Reason: These 3 commits are refactorings rather than fixes.
a6cc361e5fd anv/cmd_buffer: Advance the address when initializing clear
colors
Reason: Commit depends on earlier commit 3735af04152b which did not
land in branch.
a07f7b26198 anv/cmd_buffer: Take bo_offset into account in fast clear
state addresses
Reason: Commit addressed earlier commit a62a97933578 which did not land
in branch.
344252a27f8 i965/bufmgr: Add a helper to mark a BO as external
0a6a137eb27 i965: Mark BOs as external when we export their handle
Reason: These 2 commits addressed earlier commit 2c4097aff1b which did
not land in branch.
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
