We currently handle this by lowering it to a uniform for gen8+ but
the SPIR-V path generates this as a system value, so handle that
case as well.
---
src/mesa/drivers/dri/i965/brw_tcs.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tcs.c
b/src/mesa/drivers/dri/i965/brw_tcs.c
index 4424efea4f0..b07b11f485d 100644
--- a/src/mesa/drivers/dri/i965/brw_tcs.c
+++ b/src/mesa/drivers/dri/i965/brw_tcs.c
@@ -296,7 +296,14 @@ brw_tcs_populate_key(struct brw_context *brw,
per_patch_slots |= prog->info.patch_outputs_written;
}
- if (devinfo->gen < 8 || !tcp)
+ /* For GLSL, gen8+ lowers gl_PatchVerticesIn to a uniform, however
+ * the SPIR-V path always lowers it to a system value.
+ */
+ bool reads_patch_vertices_as_system_value =
+ tcp && (tcp->program.nir->info.system_values_read &
+ BITFIELD64_BIT(SYSTEM_VALUE_VERTICES_IN));
+
+ if (devinfo->gen < 8 || !tcp || reads_patch_vertices_as_system_value)
key->input_vertices = brw->ctx.TessCtrlProgram.patch_vertices;
key->outputs_written = per_vertex_slots;
key->patch_outputs_written = per_patch_slots;
--
2.11.0
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