From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeon/r600_buffer_common.c | 5 +----
src/gallium/drivers/radeon/r600_pipe_common.h | 2 --
src/gallium/drivers/radeonsi/si_pipe.c | 3 ---
3 files changed, 1 insertion(+), 9 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c
b/src/gallium/drivers/radeon/r600_buffer_common.c
index f0cfd09..cdcd37b 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -347,24 +347,21 @@ static void *r600_buffer_get_transfer(struct pipe_context
*ctx,
transfer->staging = staging;
*ptransfer = &transfer->b.b;
return data;
}
static bool r600_can_dma_copy_buffer(struct r600_common_context *rctx,
unsigned dstx, unsigned srcx, unsigned
size)
{
bool dword_aligned = !(dstx % 4) && !(srcx % 4) && !(size % 4);
- return rctx->screen->has_cp_dma ||
- (dword_aligned && (rctx->dma.cs ||
- rctx->screen->has_streamout));
-
+ return dword_aligned && rctx->dma.cs;
}
static void *r600_buffer_transfer_map(struct pipe_context *ctx,
struct pipe_resource *resource,
unsigned level,
unsigned usage,
const struct pipe_box *box,
struct pipe_transfer **ptransfer)
{
struct r600_common_context *rctx = (struct r600_common_context*)ctx;
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 61560ac..33332ac 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -384,22 +384,20 @@ struct r600_memory_object {
uint32_t offset;
};
struct r600_common_screen {
struct pipe_screen b;
struct radeon_winsys *ws;
enum radeon_family family;
enum chip_class chip_class;
struct radeon_info info;
uint64_t debug_flags;
- bool has_cp_dma;
- bool has_streamout;
bool has_rbplus; /* if RB+ registers
exist */
bool rbplus_allowed; /* if RB+ is allowed */
struct disk_cache *disk_shader_cache;
struct slab_parent_pool pool_transfers;
/* Texture filter settings. */
int force_aniso; /* -1 = disabled */
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index e84de36..55760fa 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1100,23 +1100,20 @@ struct pipe_screen *radeonsi_screen_create(struct
radeon_winsys *ws,
sscreen->dfsm_allowed = sscreen->dpbb_allowed &&
!(sscreen->b.debug_flags &
DBG(NO_DFSM));
}
/* While it would be nice not to have this flag, we are constrained
* by the reality that LLVM 5.0 doesn't have working VGPR indexing
* on GFX9.
*/
sscreen->llvm_has_working_vgpr_indexing = sscreen->b.chip_class <= VI;
- sscreen->b.has_cp_dma = true;
- sscreen->b.has_streamout = true;
-
/* Some chips have RB+ registers, but don't support RB+. Those must
* always disable it.
*/
if (sscreen->b.family == CHIP_STONEY ||
sscreen->b.chip_class >= GFX9) {
sscreen->b.has_rbplus = true;
sscreen->b.rbplus_allowed =
!(sscreen->b.debug_flags & DBG(NO_RB_PLUS)) &&
(sscreen->b.family == CHIP_STONEY ||
--
2.7.4
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