We were already using PTE for all render targets in case one happened to get scanned out. However, this still wasn't 100% correct because there are still possibly cases where we may want to texture from an external buffer even though we don't know the caching mode. This can happen, for instance, on buffers imported from another GPU via prime.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101691 Cc: Kenneth Graunke <kenn...@whitecape.org> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Daniel Vetter <daniel.vet...@ffwll.ch> Cc: Lyude Paul <ly...@redhat.com> --- src/mesa/drivers/dri/i965/brw_blorp.c | 7 ++++--- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 20 +++++++++++++------- 2 files changed, 17 insertions(+), 10 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 5a86af8..626bf44 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.c +++ b/src/mesa/drivers/dri/i965/brw_blorp.c @@ -114,14 +114,14 @@ brw_blorp_init(struct brw_context *brw) brw->blorp.upload_shader = brw_blorp_upload_shader; } -static uint32_t tex_mocs[] = { +static uint32_t wb_mocs[] = { [7] = GEN7_MOCS_L3, [8] = BDW_MOCS_WB, [9] = SKL_MOCS_WB, [10] = CNL_MOCS_WB, }; -static uint32_t rb_mocs[] = { +static uint32_t pte_mocs[] = { [7] = GEN7_MOCS_L3, [8] = BDW_MOCS_PTE, [9] = SKL_MOCS_PTE, @@ -158,7 +158,8 @@ blorp_surf_for_miptree(struct brw_context *brw, .buffer = mt->bo, .offset = mt->offset, .reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0, - .mocs = is_render_target ? rb_mocs[devinfo->gen] : tex_mocs[devinfo->gen], + .mocs = (is_render_target || mt->bo->external) ? pte_mocs[devinfo->gen] : + wb_mocs[devinfo->gen], }; surf->aux_usage = aux_usage; diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 27c241a..f174270 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -55,20 +55,25 @@ #include "brw_defines.h" #include "brw_wm.h" -uint32_t tex_mocs[] = { +uint32_t wb_mocs[] = { [7] = GEN7_MOCS_L3, [8] = BDW_MOCS_WB, [9] = SKL_MOCS_WB, [10] = CNL_MOCS_WB, }; -uint32_t rb_mocs[] = { +uint32_t pte_mocs[] = { [7] = GEN7_MOCS_L3, [8] = BDW_MOCS_PTE, [9] = SKL_MOCS_PTE, [10] = CNL_MOCS_PTE, }; +static inline uint32_t get_tex_mocs(struct brw_bo *bo, unsigned int gen) +{ + return (bo && bo->external ? pte_mocs : wb_mocs)[gen]; +} + static void get_isl_surf(struct brw_context *brw, struct intel_mipmap_tree *mt, GLenum target, struct isl_view *view, @@ -239,7 +244,7 @@ gen6_update_renderbuffer_surface(struct brw_context *brw, uint32_t offset; brw_emit_surface_state(brw, mt, mt->target, view, aux_usage, - rb_mocs[devinfo->gen], + pte_mocs[devinfo->gen], &offset, surf_index, RELOC_WRITE); return offset; @@ -586,7 +591,7 @@ brw_update_texture_surface(struct gl_context *ctx, aux_usage = ISL_AUX_USAGE_NONE; brw_emit_surface_state(brw, mt, mt->target, view, aux_usage, - tex_mocs[devinfo->gen], + get_tex_mocs(mt->bo, devinfo->gen), surf_offset, surf_index, 0); } @@ -617,7 +622,7 @@ brw_emit_buffer_surface_state(struct brw_context *brw, .size = buffer_size, .format = surface_format, .stride = pitch, - .mocs = tex_mocs[devinfo->gen]); + .mocs = get_tex_mocs(bo, devinfo->gen)); } void @@ -1107,7 +1112,7 @@ update_renderbuffer_read_surfaces(struct brw_context *brw) aux_usage = ISL_AUX_USAGE_NONE; brw_emit_surface_state(brw, irb->mt, target, view, aux_usage, - tex_mocs[devinfo->gen], + get_tex_mocs(irb->mt->bo, devinfo->gen), surf_offset, surf_index, 0); @@ -1599,7 +1604,8 @@ update_image_surface(struct brw_context *brw, view.base_array_layer, view.array_len)); brw_emit_surface_state(brw, mt, mt->target, view, - ISL_AUX_USAGE_NONE, tex_mocs[devinfo->gen], + ISL_AUX_USAGE_NONE, + get_tex_mocs(mt->bo, devinfo->gen), surf_offset, surf_index, access == GL_READ_ONLY ? 0 : RELOC_WRITE); } -- 2.5.0.400.gff86faf _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
