On gen7, the only 64-bit type we have is DF so we have to use that but on gen8+, we have Q types so we should use them to avoid any possibility of floating-point weirdness. While we're here, retype destinations so we aren't relying on the destination type. --- src/intel/compiler/brw_fs_nir.cpp | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index b92f158..cbd51a9 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -1411,9 +1411,18 @@ fs_visitor::nir_emit_load_const(const fs_builder &bld, break; case 64: - for (unsigned i = 0; i < instr->def.num_components; i++) - bld.MOV(offset(reg, bld, i), - setup_imm_df(bld, instr->value.f64[i])); + assert(devinfo->gen >= 7); + if (devinfo->gen == 7) { + /* We don't get 64-bit integer types until gen8 */ + for (unsigned i = 0; i < instr->def.num_components; i++) { + bld.MOV(retype(offset(reg, bld, i), BRW_REGISTER_TYPE_DF), + setup_imm_df(bld, instr->value.f64[i])); + } + } else { + for (unsigned i = 0; i < instr->def.num_components; i++) + bld.MOV(retype(offset(reg, bld, i), BRW_REGISTER_TYPE_Q), + brw_imm_q(instr->value.i64[i])); + } break; default: -- 2.5.0.400.gff86faf _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev