On 24.10.2017 19:06, Chris Wilson wrote: > Through the use of mocs, we can define the cache usage for any surface > used by the GPU. In particular, we can request that L3 cache be > allocated for either a read/write miss so that subsequent reads can be > fetched from cache rather than memory. A consequence of this is that if > we allocate a L3/LLC cacheline for a read and the object is changed in > main memory (e.g. a PCIe write bypassing the CPU) then the next read > will be serviced from the stale cache and not from the new data in > memory. This is an issue for external PRIME buffers where we may miss > the updates entirely if the image is small enough to fit within our > cache. > > Currently, we have a single bit to mark all external buffers so use that > to tell us when it is unsafe to use a cache override in mocs and > fallback to the PTE value instead (which should be set to the correct > cache level to be coherent amongst all active parties: PRIME, scanout and > render). This may be refined in future to limit the override to buffers > outside the control of mesa; as buffers being shared between mesa > clients should be able to coordinate themselves without resolves. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101691 > Cc: Kenneth Graunke <kenn...@whitecape.org> > Cc: Jason Ekstrand <ja...@jlekstrand.net> > Cc: Lyude Paul <ly...@redhat.com> > Cc: Timo Aalton <tjaal...@ubuntu.com> > Cc: Ben Widawsky <b...@bwidawsk.net> > Cc: Daniel Vetter <daniel.vet...@ffwll.ch>
This did not pass our testing, though I backported it to 17.2. Should that matter? -- t _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
