On Wed, 2017-10-25 at 16:26 -0700, Jason Ekstrand wrote:
> We have had a feature in codegen for some time that tries to
> automatically infer the execution size of an instruction from the
> width
> of its destination. For things such as fixed function GS, clipper,
> and
> SF programs, this is very useful because they tend to have lots of
> hand-rolled register setup and trying to specify the exec size all
> the
> time would be prohibitive. For things that come from a higher-level
> IR,
> however, it's easier to just set the right size all the time and the
> automatic exec sizes can, in fact, cause problems. This commit makes
> it
> optional while enabling it by default.
> ---
> src/intel/compiler/brw_eu.c | 1 +
> src/intel/compiler/brw_eu.h | 10 ++++++++++
> src/intel/compiler/brw_eu_emit.c | 32 ++++++++++++++++++----------
> ----
> 3 files changed, 29 insertions(+), 14 deletions(-)
>
> diff --git a/src/intel/compiler/brw_eu.c
> b/src/intel/compiler/brw_eu.c
> index b0bdc38..bc297a2 100644
> --- a/src/intel/compiler/brw_eu.c
> +++ b/src/intel/compiler/brw_eu.c
> @@ -296,6 +296,7 @@ brw_init_codegen(const struct gen_device_info
> *devinfo,
> memset(p, 0, sizeof(*p));
>
> p->devinfo = devinfo;
> + p->automatic_exec_sizes = true;
> /*
> * Set the initial instruction store array size to 1024, if found
> that
> * isn't enough, then it will double the store size at
> brw_next_insn()
> diff --git a/src/intel/compiler/brw_eu.h
> b/src/intel/compiler/brw_eu.h
> index 8e597b2..8abebeb 100644
> --- a/src/intel/compiler/brw_eu.h
> +++ b/src/intel/compiler/brw_eu.h
> @@ -65,6 +65,16 @@ struct brw_codegen {
> bool compressed_stack[BRW_EU_MAX_INSN_STACK];
> brw_inst *current;
>
> + /** Whether or not the user wants automatic exec sizes
> + *
> + * If true, codegen will try to automatically infer the exec size
> of an
> + * instruction from the width of the destination register. If
> false, it
> + * will take whatever is set by brw_set_default_exec_size
> verbatim.
> + *
> + * This is set to true by default in brw_init_codegen.
> + */
> + bool automatic_exec_sizes;
> +
> bool single_program_flow;
> const struct gen_device_info *devinfo;
>
> diff --git a/src/intel/compiler/brw_eu_emit.c
> b/src/intel/compiler/brw_eu_emit.c
> index fae74cf..902914f 100644
> --- a/src/intel/compiler/brw_eu_emit.c
> +++ b/src/intel/compiler/brw_eu_emit.c
> @@ -141,22 +141,26 @@ brw_set_dest(struct brw_codegen *p, brw_inst
> *inst, struct brw_reg dest)
>
> /* Generators should set a default exec_size of either 8 (SIMD4x2
> or SIMD8)
> * or 16 (SIMD16), as that's normally correct. However, when
> dealing with
> - * small registers, we automatically reduce it to match the
> register size.
> - *
> - * In platforms that support fp64 we can emit instructions with a
> width of
> - * 4 that need two SIMD8 registers and an exec_size of 8 or 16.
> In these
> - * cases we need to make sure that these instructions have their
> exec sizes
> - * set properly when they are emitted and we can't rely on this
> code to fix
> - * it.
> + * small registers, it can be useful for us toautomatically
to automatically
> reduce it to
> + * match the register size.
> */
> - bool fix_exec_size;
> - if (devinfo->gen >= 6)
> - fix_exec_size = dest.width < BRW_EXECUTE_4;
> - else
> - fix_exec_size = dest.width < BRW_EXECUTE_8;
> + if (p->automatic_exec_sizes) {
> + /*
> + * In platforms that support fp64 we can emit instructions
> with a width
> + * of 4 that need two SIMD8 registers and an exec_size of 8 or
> 16. In
> + * these cases we need to make sure that these instructions
> have their
> + * exec sizes set properly when they are emitted and we can't
> rely on
> + * this code to fix it.
> + */
> + bool fix_exec_size;
> + if (devinfo->gen >= 6)
> + fix_exec_size = dest.width < BRW_EXECUTE_4;
> + else
> + fix_exec_size = dest.width < BRW_EXECUTE_8;
>
> - if (fix_exec_size)
> - brw_inst_set_exec_size(devinfo, inst, dest.width);
> + if (fix_exec_size)
> + brw_inst_set_exec_size(devinfo, inst, dest.width);
> + }
> }
>
> void
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