This isn't often a problem , when we're in a compute shader, we must
push the thread local ID so we decrement the amount of available push
space by 1 and it's no longer even and 64-bit data can, in theory, span
it. By marking those uniforms contiguous, we ensure that they never get
split in half between push and pull constants.
Cc: mesa-sta...@lists.freedesktop.org
---
src/intel/compiler/brw_fs.cpp | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 385f500..39a9e21 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -1974,7 +1974,7 @@ fs_visitor::assign_constant_locations()
/* For each uniform slot, a value of true indicates that the given slot and
* the next slot must remain contiguous. This is used to keep us from
- * splitting arrays apart.
+ * splitting arrays and 64-bit values apart.
*/
bool contiguous[uniforms];
memset(contiguous, 0, sizeof(contiguous));
@@ -2011,6 +2011,9 @@ fs_visitor::assign_constant_locations()
if (constant_nr >= 0 && constant_nr < (int) uniforms) {
int regs_read = inst->components_read(i) *
type_sz(inst->src[i].type) / 4;
+ assert(regs_read <= 2);
+ if (regs_read == 2)
+ contiguous[constant_nr] = true;
for (int j = 0; j < regs_read; j++) {
is_live[constant_nr + j] = true;
bitsize_access[constant_nr + j] =
--
2.5.0.400.gff86faf
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