---
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 34 +++++++++++++--------------
src/gallium/winsys/amdgpu/drm/amdgpu_bo.h | 2 +-
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 20 ++++++++--------
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 28 +++++++++++-----------
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h | 5 ++--
5 files changed, 45 insertions(+), 44 deletions(-)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 897b4f0596..8c591110bb 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -87,70 +87,70 @@ static bool amdgpu_bo_wait(struct pb_buffer *_buf, uint64_t
timeout,
if (r)
fprintf(stderr, "%s: amdgpu_bo_wait_for_idle failed %i\n", __func__,
r);
return !buffer_busy;
}
if (timeout == 0) {
unsigned idle_fences;
bool buffer_idle;
- mtx_lock(&ws->bo_fence_lock);
+ simple_mtx_lock(&ws->bo_fence_lock);
for (idle_fences = 0; idle_fences < bo->num_fences; ++idle_fences) {
if (!amdgpu_fence_wait(bo->fences[idle_fences], 0, false))
break;
}
/* Release the idle fences to avoid checking them again later. */
for (unsigned i = 0; i < idle_fences; ++i)
amdgpu_fence_reference(&bo->fences[i], NULL);
memmove(&bo->fences[0], &bo->fences[idle_fences],
(bo->num_fences - idle_fences) * sizeof(*bo->fences));
bo->num_fences -= idle_fences;
buffer_idle = !bo->num_fences;
- mtx_unlock(&ws->bo_fence_lock);
+ simple_mtx_unlock(&ws->bo_fence_lock);
return buffer_idle;
} else {
bool buffer_idle = true;
- mtx_lock(&ws->bo_fence_lock);
+ simple_mtx_lock(&ws->bo_fence_lock);
while (bo->num_fences && buffer_idle) {
struct pipe_fence_handle *fence = NULL;
bool fence_idle = false;
amdgpu_fence_reference(&fence, bo->fences[0]);
/* Wait for the fence. */
- mtx_unlock(&ws->bo_fence_lock);
+ simple_mtx_unlock(&ws->bo_fence_lock);
if (amdgpu_fence_wait(fence, abs_timeout, true))
fence_idle = true;
else
buffer_idle = false;
- mtx_lock(&ws->bo_fence_lock);
+ simple_mtx_lock(&ws->bo_fence_lock);
/* Release an idle fence to avoid checking it again later, keeping in
* mind that the fence array may have been modified by other threads.
*/
if (fence_idle && bo->num_fences && bo->fences[0] == fence) {
amdgpu_fence_reference(&bo->fences[0], NULL);
memmove(&bo->fences[0], &bo->fences[1],
(bo->num_fences - 1) * sizeof(*bo->fences));
bo->num_fences--;
}
amdgpu_fence_reference(&fence, NULL);
}
- mtx_unlock(&ws->bo_fence_lock);
+ simple_mtx_unlock(&ws->bo_fence_lock);
return buffer_idle;
}
}
static enum radeon_bo_domain amdgpu_bo_get_initial_domain(
struct pb_buffer *buf)
{
return ((struct amdgpu_winsys_bo*)buf)->initial_domain;
}
@@ -165,24 +165,24 @@ static void amdgpu_bo_remove_fences(struct
amdgpu_winsys_bo *bo)
bo->max_fences = 0;
}
void amdgpu_bo_destroy(struct pb_buffer *_buf)
{
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
assert(bo->bo && "must not be called for slab entries");
if (bo->ws->debug_all_bos) {
- mtx_lock(&bo->ws->global_bo_list_lock);
+ simple_mtx_lock(&bo->ws->global_bo_list_lock);
LIST_DEL(&bo->u.real.global_list_item);
bo->ws->num_buffers--;
- mtx_unlock(&bo->ws->global_bo_list_lock);
+ simple_mtx_unlock(&bo->ws->global_bo_list_lock);
}
amdgpu_bo_va_op(bo->bo, 0, bo->base.size, bo->va, 0, AMDGPU_VA_OP_UNMAP);
amdgpu_va_range_free(bo->u.real.va_handle);
amdgpu_bo_free(bo->bo);
amdgpu_bo_remove_fences(bo);
if (bo->initial_domain & RADEON_DOMAIN_VRAM)
bo->ws->allocated_vram -= align64(bo->base.size,
bo->ws->info.gart_page_size);
@@ -360,24 +360,24 @@ static const struct pb_vtbl amdgpu_winsys_bo_vtbl = {
/* other functions are never called */
};
static void amdgpu_add_buffer_to_global_list(struct amdgpu_winsys_bo *bo)
{
struct amdgpu_winsys *ws = bo->ws;
assert(bo->bo);
if (ws->debug_all_bos) {
- mtx_lock(&ws->global_bo_list_lock);
+ simple_mtx_lock(&ws->global_bo_list_lock);
LIST_ADDTAIL(&bo->u.real.global_list_item, &ws->global_bo_list);
ws->num_buffers++;
- mtx_unlock(&ws->global_bo_list_lock);
+ simple_mtx_unlock(&ws->global_bo_list_lock);
}
}
static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *ws,
uint64_t size,
unsigned alignment,
unsigned usage,
enum radeon_bo_domain
initial_domain,
unsigned flags,
unsigned pb_cache_bucket)
@@ -719,23 +719,23 @@ sparse_backing_alloc(struct amdgpu_winsys_bo *bo,
uint32_t *pstart_page, uint32_
}
static void
sparse_free_backing_buffer(struct amdgpu_winsys_bo *bo,
struct amdgpu_sparse_backing *backing)
{
struct amdgpu_winsys *ws = backing->bo->ws;
bo->u.sparse.num_backing_pages -= backing->bo->base.size /
RADEON_SPARSE_PAGE_SIZE;
- mtx_lock(&ws->bo_fence_lock);
+ simple_mtx_lock(&ws->bo_fence_lock);
amdgpu_add_fences(backing->bo, bo->num_fences, bo->fences);
- mtx_unlock(&ws->bo_fence_lock);
+ simple_mtx_unlock(&ws->bo_fence_lock);
list_del(&backing->list);
amdgpu_winsys_bo_reference(&backing->bo, NULL);
FREE(backing->chunks);
FREE(backing);
}
/*
* Return a range of pages from the given backing buffer back into the
* free structure.
@@ -816,21 +816,21 @@ static void amdgpu_bo_sparse_destroy(struct pb_buffer
*_buf)
}
while (!list_empty(&bo->u.sparse.backing)) {
struct amdgpu_sparse_backing *dummy = NULL;
sparse_free_backing_buffer(bo,
container_of(bo->u.sparse.backing.next,
dummy, list));
}
amdgpu_va_range_free(bo->u.sparse.va_handle);
- mtx_destroy(&bo->u.sparse.commit_lock);
+ simple_mtx_destroy(&bo->u.sparse.commit_lock);
FREE(bo->u.sparse.commitments);
FREE(bo);
}
static const struct pb_vtbl amdgpu_winsys_bo_sparse_vtbl = {
amdgpu_bo_sparse_destroy
/* other functions are never called */
};
static struct pb_buffer *
@@ -863,21 +863,21 @@ amdgpu_bo_sparse_create(struct amdgpu_winsys *ws,
uint64_t size,
bo->unique_id = __sync_fetch_and_add(&ws->next_bo_unique_id, 1);
bo->sparse = true;
bo->u.sparse.flags = flags & ~RADEON_FLAG_SPARSE;
bo->u.sparse.num_va_pages = DIV_ROUND_UP(size, RADEON_SPARSE_PAGE_SIZE);
bo->u.sparse.commitments = CALLOC(bo->u.sparse.num_va_pages,
sizeof(*bo->u.sparse.commitments));
if (!bo->u.sparse.commitments)
goto error_alloc_commitments;
- mtx_init(&bo->u.sparse.commit_lock, mtx_plain);
+ simple_mtx_init(&bo->u.sparse.commit_lock, mtx_plain);
LIST_INITHEAD(&bo->u.sparse.backing);
/* For simplicity, we always map a multiple of the page size. */
map_size = align64(size, RADEON_SPARSE_PAGE_SIZE);
va_gap_size = ws->check_vm ? 4 * RADEON_SPARSE_PAGE_SIZE : 0;
r = amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general,
map_size + va_gap_size, RADEON_SPARSE_PAGE_SIZE,
0, &bo->va, &bo->u.sparse.va_handle, 0);
if (r)
goto error_va_alloc;
@@ -885,21 +885,21 @@ amdgpu_bo_sparse_create(struct amdgpu_winsys *ws,
uint64_t size,
r = amdgpu_bo_va_op_raw(bo->ws->dev, NULL, 0, size, bo->va,
AMDGPU_VM_PAGE_PRT, AMDGPU_VA_OP_MAP);
if (r)
goto error_va_map;
return &bo->base;
error_va_map:
amdgpu_va_range_free(bo->u.sparse.va_handle);
error_va_alloc:
- mtx_destroy(&bo->u.sparse.commit_lock);
+ simple_mtx_destroy(&bo->u.sparse.commit_lock);
FREE(bo->u.sparse.commitments);
error_alloc_commitments:
FREE(bo);
return NULL;
}
static bool
amdgpu_bo_sparse_commit(struct pb_buffer *buf, uint64_t offset, uint64_t size,
bool commit)
{
@@ -912,21 +912,21 @@ amdgpu_bo_sparse_commit(struct pb_buffer *buf, uint64_t
offset, uint64_t size,
assert(bo->sparse);
assert(offset % RADEON_SPARSE_PAGE_SIZE == 0);
assert(offset <= bo->base.size);
assert(size <= bo->base.size - offset);
assert(size % RADEON_SPARSE_PAGE_SIZE == 0 || offset + size ==
bo->base.size);
comm = bo->u.sparse.commitments;
va_page = offset / RADEON_SPARSE_PAGE_SIZE;
end_va_page = va_page + DIV_ROUND_UP(size, RADEON_SPARSE_PAGE_SIZE);
- mtx_lock(&bo->u.sparse.commit_lock);
+ simple_mtx_lock(&bo->u.sparse.commit_lock);
#if DEBUG_SPARSE_COMMITS
sparse_dump(bo, __func__);
#endif
if (commit) {
while (va_page < end_va_page) {
uint32_t span_va_page;
/* Skip pages that are already committed. */
@@ -1016,21 +1016,21 @@ amdgpu_bo_sparse_commit(struct pb_buffer *buf, uint64_t
offset, uint64_t size,
if (!sparse_backing_free(bo, backing, backing_start, span_pages)) {
/* Couldn't allocate tracking data structures, so we have to leak
*/
fprintf(stderr, "amdgpu: leaking PRT backing memory\n");
ok = false;
}
}
}
out:
- mtx_unlock(&bo->u.sparse.commit_lock);
+ simple_mtx_unlock(&bo->u.sparse.commit_lock);
return ok;
}
static unsigned eg_tile_split(unsigned tile_split)
{
switch (tile_split) {
case 0: tile_split = 64; break;
case 1: tile_split = 128; break;
case 2: tile_split = 256; break;
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
index 10b095d7a1..a0f2b01c43 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
@@ -69,21 +69,21 @@ struct amdgpu_winsys_bo {
int map_count;
bool use_reusable_pool;
struct list_head global_list_item;
} real;
struct {
struct pb_slab_entry entry;
struct amdgpu_winsys_bo *real;
} slab;
struct {
- mtx_t commit_lock;
+ simple_mtx_t commit_lock;
amdgpu_va_handle va_handle;
enum radeon_bo_flag flags;
uint32_t num_va_pages;
uint32_t num_backing_pages;
struct list_head backing;
/* Commitment information for each page of the virtual memory area. */
struct amdgpu_sparse_commitment *commitments;
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 768a1640c1..efa113a081 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -464,30 +464,30 @@ static int amdgpu_lookup_or_add_sparse_buffer(struct
amdgpu_cs *acs,
amdgpu_winsys_bo_reference(&buffer->bo, bo);
p_atomic_inc(&bo->num_cs_references);
cs->num_sparse_buffers++;
hash = bo->unique_id & (ARRAY_SIZE(cs->buffer_indices_hashlist)-1);
cs->buffer_indices_hashlist[hash] = idx;
/* We delay adding the backing buffers until we really have to. However,
* we cannot delay accounting for memory use.
*/
- mtx_lock(&bo->u.sparse.commit_lock);
+ simple_mtx_lock(&bo->u.sparse.commit_lock);
list_for_each_entry(struct amdgpu_sparse_backing, backing,
&bo->u.sparse.backing, list) {
if (bo->initial_domain & RADEON_DOMAIN_VRAM)
acs->main.base.used_vram += backing->bo->base.size;
else if (bo->initial_domain & RADEON_DOMAIN_GTT)
acs->main.base.used_gart += backing->bo->base.size;
}
- mtx_unlock(&bo->u.sparse.commit_lock);
+ simple_mtx_unlock(&bo->u.sparse.commit_lock);
return idx;
}
static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs *rcs,
struct pb_buffer *buf,
enum radeon_bo_usage usage,
enum radeon_bo_domain domains,
enum radeon_bo_priority priority)
{
@@ -1055,39 +1055,39 @@ static void
amdgpu_add_fence_dependencies_bo_lists(struct amdgpu_cs *acs)
*
* This is done late, during submission, to keep the buffer list short before
* submit, and to avoid managing fences for the backing buffers.
*/
static bool amdgpu_add_sparse_backing_buffers(struct amdgpu_cs_context *cs)
{
for (unsigned i = 0; i < cs->num_sparse_buffers; ++i) {
struct amdgpu_cs_buffer *buffer = &cs->sparse_buffers[i];
struct amdgpu_winsys_bo *bo = buffer->bo;
- mtx_lock(&bo->u.sparse.commit_lock);
+ simple_mtx_lock(&bo->u.sparse.commit_lock);
list_for_each_entry(struct amdgpu_sparse_backing, backing,
&bo->u.sparse.backing, list) {
/* We can directly add the buffer here, because we know that each
* backing buffer occurs only once.
*/
int idx = amdgpu_do_add_real_buffer(cs, backing->bo);
if (idx < 0) {
fprintf(stderr, "%s: failed to add buffer\n", __FUNCTION__);
- mtx_unlock(&bo->u.sparse.commit_lock);
+ simple_mtx_unlock(&bo->u.sparse.commit_lock);
return false;
}
cs->real_buffers[idx].usage = buffer->usage &
~RADEON_USAGE_SYNCHRONIZED;
cs->real_buffers[idx].u.real.priority_usage =
buffer->u.real.priority_usage;
p_atomic_inc(&backing->bo->num_active_ioctls);
}
- mtx_unlock(&bo->u.sparse.commit_lock);
+ simple_mtx_unlock(&bo->u.sparse.commit_lock);
}
return true;
}
void amdgpu_cs_submit_ib(void *job, int thread_index)
{
struct amdgpu_cs *acs = (struct amdgpu_cs*)job;
struct amdgpu_winsys *ws = acs->ctx->ws;
struct amdgpu_cs_context *cs = acs->cst;
@@ -1097,39 +1097,39 @@ void amdgpu_cs_submit_ib(void *job, int thread_index)
bool has_user_fence = amdgpu_cs_has_user_fence(cs);
/* Create the buffer list.
* Use a buffer list containing all allocated buffers if requested.
*/
if (ws->debug_all_bos) {
struct amdgpu_winsys_bo *bo;
amdgpu_bo_handle *handles;
unsigned num = 0;
- mtx_lock(&ws->global_bo_list_lock);
+ simple_mtx_lock(&ws->global_bo_list_lock);
handles = malloc(sizeof(handles[0]) * ws->num_buffers);
if (!handles) {
- mtx_unlock(&ws->global_bo_list_lock);
+ simple_mtx_unlock(&ws->global_bo_list_lock);
amdgpu_cs_context_cleanup(cs);
cs->error_code = -ENOMEM;
return;
}
LIST_FOR_EACH_ENTRY(bo, &ws->global_bo_list, u.real.global_list_item) {
assert(num < ws->num_buffers);
handles[num++] = bo->bo;
}
r = amdgpu_bo_list_create(ws->dev, ws->num_buffers,
handles, NULL, &bo_list);
free(handles);
- mtx_unlock(&ws->global_bo_list_lock);
+ simple_mtx_unlock(&ws->global_bo_list_lock);
} else {
unsigned num_handles;
if (!amdgpu_add_sparse_backing_buffers(cs)) {
r = -ENOMEM;
goto bo_list_error;
}
if (cs->max_real_submit < cs->num_real_buffers) {
FREE(cs->handles);
@@ -1346,32 +1346,32 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
amdgpu_fence_reference(fence, cur->fence);
amdgpu_cs_sync_flush(rcs);
/* Prepare buffers.
*
* This fence must be held until the submission is queued to ensure
* that the order of fence dependency updates matches the order of
* submissions.
*/
- mtx_lock(&ws->bo_fence_lock);
+ simple_mtx_lock(&ws->bo_fence_lock);
amdgpu_add_fence_dependencies_bo_lists(cs);
/* Swap command streams. "cst" is going to be submitted. */
cs->csc = cs->cst;
cs->cst = cur;
/* Submit. */
util_queue_add_job(&ws->cs_queue, cs, &cs->flush_completed,
amdgpu_cs_submit_ib, NULL);
/* The submission has been queued, unlock the fence now. */
- mtx_unlock(&ws->bo_fence_lock);
+ simple_mtx_unlock(&ws->bo_fence_lock);
if (!(flags & RADEON_FLUSH_ASYNC)) {
amdgpu_cs_sync_flush(rcs);
error_code = cur->error_code;
}
} else {
amdgpu_cs_context_cleanup(cs->csc);
}
amdgpu_get_new_ib(&ws->base, cs, IB_MAIN);
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
index 5e0c1fd8d8..2657609b0d 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
@@ -41,21 +41,21 @@
#include <sys/stat.h>
#include "amd/common/amdgpu_id.h"
#include "amd/common/sid.h"
#include "amd/common/gfx9d.h"
#ifndef AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS
#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
#endif
static struct util_hash_table *dev_tab = NULL;
-static mtx_t dev_tab_mutex = _MTX_INITIALIZER_NP;
+static simple_mtx_t dev_tab_mutex = _SIMPLE_MTX_INITIALIZER_NP;
DEBUG_GET_ONCE_BOOL_OPTION(all_bos, "RADEON_ALL_BOS", false)
/* Helper function to do the ioctls needed for setup and init. */
static bool do_winsys_init(struct amdgpu_winsys *ws, int fd)
{
if (!ac_query_gpu_info(fd, ws->dev, &ws->info, &ws->amdinfo))
goto fail;
/* LLVM 5.0 is required for GFX9. */
@@ -88,24 +88,24 @@ static void do_winsys_deinit(struct amdgpu_winsys *ws)
amdgpu_device_deinitialize(ws->dev);
}
static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
{
struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
if (util_queue_is_initialized(&ws->cs_queue))
util_queue_destroy(&ws->cs_queue);
- mtx_destroy(&ws->bo_fence_lock);
+ simple_mtx_destroy(&ws->bo_fence_lock);
pb_slabs_deinit(&ws->bo_slabs);
pb_cache_deinit(&ws->bo_cache);
- mtx_destroy(&ws->global_bo_list_lock);
+ simple_mtx_destroy(&ws->global_bo_list_lock);
do_winsys_deinit(ws);
FREE(rws);
}
static void amdgpu_winsys_query_info(struct radeon_winsys *rws,
struct radeon_info *info)
{
*info = ((struct amdgpu_winsys *)rws)->info;
}
@@ -209,27 +209,27 @@ static int compare_dev(void *key1, void *key2)
static bool amdgpu_winsys_unref(struct radeon_winsys *rws)
{
struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
bool destroy;
/* When the reference counter drops to zero, remove the device pointer
* from the table.
* This must happen while the mutex is locked, so that
* amdgpu_winsys_create in another thread doesn't get the winsys
* from the table when the counter drops to 0. */
- mtx_lock(&dev_tab_mutex);
+ simple_mtx_lock(&dev_tab_mutex);
destroy = pipe_reference(&ws->reference, NULL);
if (destroy && dev_tab)
util_hash_table_remove(dev_tab, ws->dev);
- mtx_unlock(&dev_tab_mutex);
+ simple_mtx_unlock(&dev_tab_mutex);
return destroy;
}
static const char* amdgpu_get_chip_name(struct radeon_winsys *ws)
{
amdgpu_device_handle dev = ((struct amdgpu_winsys *)ws)->dev;
return amdgpu_get_marketing_name(dev);
}
@@ -243,38 +243,38 @@ amdgpu_winsys_create(int fd, const struct
pipe_screen_config *config,
uint32_t drm_major, drm_minor, r;
/* The DRM driver version of amdgpu is 3.x.x. */
if (version->version_major != 3) {
drmFreeVersion(version);
return NULL;
}
drmFreeVersion(version);
/* Look up the winsys from the dev table. */
- mtx_lock(&dev_tab_mutex);
+ simple_mtx_lock(&dev_tab_mutex);
if (!dev_tab)
dev_tab = util_hash_table_create(hash_dev, compare_dev);
/* Initialize the amdgpu device. This should always return the same pointer
* for the same fd. */
r = amdgpu_device_initialize(fd, &drm_major, &drm_minor, &dev);
if (r) {
- mtx_unlock(&dev_tab_mutex);
+ simple_mtx_unlock(&dev_tab_mutex);
fprintf(stderr, "amdgpu: amdgpu_device_initialize failed.\n");
return NULL;
}
/* Lookup a winsys if we have already created one for this device. */
ws = util_hash_table_get(dev_tab, dev);
if (ws) {
pipe_reference(NULL, &ws->reference);
- mtx_unlock(&dev_tab_mutex);
+ simple_mtx_unlock(&dev_tab_mutex);
return &ws->base;
}
/* Create a new winsys. */
ws = CALLOC_STRUCT(amdgpu_winsys);
if (!ws)
goto fail;
ws->dev = dev;
ws->info.drm_major = drm_major;
@@ -309,50 +309,50 @@ amdgpu_winsys_create(int fd, const struct
pipe_screen_config *config,
ws->base.cs_request_feature = amdgpu_cs_request_feature;
ws->base.query_value = amdgpu_query_value;
ws->base.read_registers = amdgpu_read_registers;
ws->base.get_chip_name = amdgpu_get_chip_name;
amdgpu_bo_init_functions(ws);
amdgpu_cs_init_functions(ws);
amdgpu_surface_init_functions(ws);
LIST_INITHEAD(&ws->global_bo_list);
- (void) mtx_init(&ws->global_bo_list_lock, mtx_plain);
- (void) mtx_init(&ws->bo_fence_lock, mtx_plain);
+ (void) simple_mtx_init(&ws->global_bo_list_lock, mtx_plain);
+ (void) simple_mtx_init(&ws->bo_fence_lock, mtx_plain);
if (!util_queue_init(&ws->cs_queue, "amdgpu_cs", 8, 1,
UTIL_QUEUE_INIT_RESIZE_IF_FULL)) {
amdgpu_winsys_destroy(&ws->base);
- mtx_unlock(&dev_tab_mutex);
+ simple_mtx_unlock(&dev_tab_mutex);
return NULL;
}
/* Create the screen at the end. The winsys must be initialized
* completely.
*
* Alternatively, we could create the screen based on "ws->gen"
* and link all drivers into one binary blob. */
ws->base.screen = screen_create(&ws->base, config);
if (!ws->base.screen) {
amdgpu_winsys_destroy(&ws->base);
- mtx_unlock(&dev_tab_mutex);
+ simple_mtx_unlock(&dev_tab_mutex);
return NULL;
}
util_hash_table_set(dev_tab, dev, ws);
/* We must unlock the mutex once the winsys is fully initialized, so that
* other threads attempting to create the winsys from the same fd will
* get a fully initialized winsys and not just half-way initialized. */
- mtx_unlock(&dev_tab_mutex);
+ simple_mtx_unlock(&dev_tab_mutex);
return &ws->base;
fail_cache:
pb_cache_deinit(&ws->bo_cache);
do_winsys_deinit(ws);
fail_alloc:
FREE(ws);
fail:
- mtx_unlock(&dev_tab_mutex);
+ simple_mtx_unlock(&dev_tab_mutex);
return NULL;
}
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
index de54470ede..b7af68527a 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
@@ -29,38 +29,39 @@
* Marek Olšák <mar...@gmail.com>
*/
#ifndef AMDGPU_WINSYS_H
#define AMDGPU_WINSYS_H
#include "pipebuffer/pb_cache.h"
#include "pipebuffer/pb_slab.h"
#include "gallium/drivers/radeon/radeon_winsys.h"
#include "addrlib/addrinterface.h"
+#include "util/simple_mtx.h"
#include "util/u_queue.h"
#include <amdgpu.h>
struct amdgpu_cs;
#define AMDGPU_SLAB_MIN_SIZE_LOG2 9 /* 512 bytes */
#define AMDGPU_SLAB_MAX_SIZE_LOG2 16 /* 64 KB */
#define AMDGPU_SLAB_BO_SIZE_LOG2 17 /* 128 KB */
struct amdgpu_winsys {
struct radeon_winsys base;
struct pipe_reference reference;
struct pb_cache bo_cache;
struct pb_slabs bo_slabs;
amdgpu_device_handle dev;
- mtx_t bo_fence_lock;
+ simple_mtx_t bo_fence_lock;
int num_cs; /* The number of command streams created. */
unsigned num_total_rejected_cs;
uint32_t surf_index_color;
uint32_t surf_index_fmask;
uint32_t next_bo_unique_id;
uint64_t allocated_vram;
uint64_t allocated_gtt;
uint64_t mapped_vram;
uint64_t mapped_gtt;
@@ -75,21 +76,21 @@ struct amdgpu_winsys {
/* multithreaded IB submission */
struct util_queue cs_queue;
struct amdgpu_gpu_info amdinfo;
ADDR_HANDLE addrlib;
bool check_vm;
bool debug_all_bos;
/* List of all allocated buffers */
- mtx_t global_bo_list_lock;
+ simple_mtx_t global_bo_list_lock;
struct list_head global_bo_list;
unsigned num_buffers;
};
static inline struct amdgpu_winsys *
amdgpu_winsys(struct radeon_winsys *base)
{
return (struct amdgpu_winsys*)base;
}
--
2.13.6
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