From: Marek Olšák <marek.ol...@amd.com>
---
src/amd/common/ac_surface.c | 10 ++++++++++
src/amd/common/ac_surface.h | 2 ++
2 files changed, 12 insertions(+)
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 22c653f..821ad56 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -788,20 +788,22 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
surf->dcc_alignment * 4);
}
/* Make sure HTILE covers the whole miptree, because the shader reads
* TC-compatible HTILE even for levels where it's disabled by DB.
*/
if (surf->htile_size && config->info.levels > 1)
surf->htile_size *= 2;
surf->is_linear = surf->u.legacy.level[0].mode ==
RADEON_SURF_MODE_LINEAR_ALIGNED;
+ surf->is_displayable = surf->micro_tile_mode ==
RADEON_MICRO_MODE_DISPLAY ||
+ surf->micro_tile_mode ==
RADEON_MICRO_MODE_ROTATED;
return 0;
}
/* This is only called when expecting a tiled layout. */
static int
gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
bool is_fmask, AddrSwizzleMode *swizzle_mode)
{
ADDR_E_RETURNCODE ret;
@@ -1149,20 +1151,28 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
} else
AddrSurfInfoIn.flags.depth = 0;
r = gfx9_compute_miptree(addrlib, surf, compressed,
&AddrSurfInfoIn);
if (r)
return r;
}
surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
+ /* Query whether the surface is displayable. */
+ bool displayable = false;
+ r = Addr2IsValidDisplaySwizzleMode(addrlib,
surf->u.gfx9.surf.swizzle_mode,
+ surf->bpe * 8, &displayable);
+ if (r)
+ return r;
+ surf->is_displayable = displayable;
+
switch (surf->u.gfx9.surf.swizzle_mode) {
/* S = standard. */
case ADDR_SW_256B_S:
case ADDR_SW_4KB_S:
case ADDR_SW_64KB_S:
case ADDR_SW_VAR_S:
case ADDR_SW_64KB_S_T:
case ADDR_SW_4KB_S_X:
case ADDR_SW_64KB_S_X:
case ADDR_SW_VAR_S_X:
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 96138b9..7ac4737 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -154,20 +154,22 @@ struct radeon_surf {
unsigned blk_w:4;
unsigned blk_h:4;
unsigned bpe:5;
/* Number of mipmap levels where DCC is enabled starting from level 0.
* Non-zero levels may be disabled due to alignment constraints, but not
* the first level.
*/
unsigned num_dcc_levels:4;
unsigned is_linear:1;
unsigned has_stencil:1;
+ /* This might be true even if micro_tile_mode isn't displayable or
rotated. */
+ unsigned is_displayable:1;
/* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */
unsigned micro_tile_mode:3;
uint32_t flags;
/* These are return values. Some of them can be set by the caller, but
* they will be treated as hints (e.g. bankw, bankh) and might be
* changed by the calculator.
*/
/* Tile swizzle can be OR'd with low bits of the BASE_256B address.
--
2.7.4
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