From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeonsi/si_shader.c | 23 ++++++++++++++---------
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index c0037fe..c6cb45b 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -4180,28 +4180,27 @@ static void declare_per_stage_desc_pointers(struct
si_shader_context *ctx,
add_arg(fninfo, ARG_SGPR,
si_const_array(ctx->v8i32,
SI_NUM_IMAGES + SI_NUM_SAMPLERS * 2));
if (assign_params) {
ctx->param_const_and_shader_buffers = const_and_shader_buffers;
ctx->param_samplers_and_images = samplers_and_images;
}
}
-static void declare_default_desc_pointers(struct si_shader_context *ctx,
- struct si_function_info *fninfo)
+static void declare_global_desc_pointers(struct si_shader_context *ctx,
+ struct si_function_info *fninfo)
{
ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS));
ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
si_const_array(ctx->v8i32, 0));
- declare_per_stage_desc_pointers(ctx, fninfo, true);
}
static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
struct si_function_info *fninfo)
{
ctx->param_vertex_buffers = add_arg(fninfo, ARG_SGPR,
si_const_array(ctx->v4i32, SI_NUM_VERTEX_BUFFERS));
add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
@@ -4265,21 +4264,22 @@ static void create_function(struct si_shader_context
*ctx)
if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
}
LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
switch (type) {
case PIPE_SHADER_VERTEX:
- declare_default_desc_pointers(ctx, &fninfo);
+ declare_global_desc_pointers(ctx, &fninfo);
+ declare_per_stage_desc_pointers(ctx, &fninfo, true);
declare_vs_specific_input_sgprs(ctx, &fninfo);
if (shader->key.as_es) {
assert(!shader->selector->nir);
ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
} else if (shader->key.as_ls) {
assert(!shader->selector->nir);
/* no extra parameters */
} else {
if (shader->is_gs_copy_shader) {
@@ -4290,21 +4290,22 @@ static void create_function(struct si_shader_context
*ctx)
/* The locations of the other parameters are assigned
dynamically. */
declare_streamout_params(ctx, &shader->selector->so,
&fninfo);
}
/* VGPRs */
declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
break;
case PIPE_SHADER_TESS_CTRL: /* SI-CI-VI */
- declare_default_desc_pointers(ctx, &fninfo);
+ declare_global_desc_pointers(ctx, &fninfo);
+ declare_per_stage_desc_pointers(ctx, &fninfo, true);
ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo,
ARG_SGPR, ctx->i32);
ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
/* VGPRs */
@@ -4432,57 +4433,60 @@ static void create_function(struct si_shader_context
*ctx)
ctx->type == PIPE_SHADER_TESS_EVAL) {
/* ES return values are inputs to GS. */
for (i = 0; i < 8 + GFX9_GS_NUM_USER_SGPR; i++)
returns[num_returns++] = ctx->i32; /* SGPRs */
for (i = 0; i < 5; i++)
returns[num_returns++] = ctx->f32; /* VGPRs */
}
break;
case PIPE_SHADER_TESS_EVAL:
- declare_default_desc_pointers(ctx, &fninfo);
+ declare_global_desc_pointers(ctx, &fninfo);
+ declare_per_stage_desc_pointers(ctx, &fninfo, true);
ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo,
ARG_SGPR, ctx->i32);
if (shader->key.as_es) {
ctx->param_tcs_offchip_offset = add_arg(&fninfo,
ARG_SGPR, ctx->i32);
add_arg(&fninfo, ARG_SGPR, ctx->i32);
ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
} else {
add_arg(&fninfo, ARG_SGPR, ctx->i32);
declare_streamout_params(ctx, &shader->selector->so,
&fninfo);
ctx->param_tcs_offchip_offset = add_arg(&fninfo,
ARG_SGPR, ctx->i32);
}
/* VGPRs */
declare_tes_input_vgprs(ctx, &fninfo);
break;
case PIPE_SHADER_GEOMETRY:
- declare_default_desc_pointers(ctx, &fninfo);
+ declare_global_desc_pointers(ctx, &fninfo);
+ declare_per_stage_desc_pointers(ctx, &fninfo, true);
ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
/* VGPRs */
ctx->param_gs_vtx0_offset = add_arg(&fninfo, ARG_VGPR,
ctx->i32);
ctx->param_gs_vtx1_offset = add_arg(&fninfo, ARG_VGPR,
ctx->i32);
ctx->param_gs_prim_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
ctx->param_gs_vtx2_offset = add_arg(&fninfo, ARG_VGPR,
ctx->i32);
ctx->param_gs_vtx3_offset = add_arg(&fninfo, ARG_VGPR,
ctx->i32);
ctx->param_gs_vtx4_offset = add_arg(&fninfo, ARG_VGPR,
ctx->i32);
ctx->param_gs_vtx5_offset = add_arg(&fninfo, ARG_VGPR,
ctx->i32);
ctx->param_gs_instance_id = add_arg(&fninfo, ARG_VGPR,
ctx->i32);
break;
case PIPE_SHADER_FRAGMENT:
- declare_default_desc_pointers(ctx, &fninfo);
+ declare_global_desc_pointers(ctx, &fninfo);
+ declare_per_stage_desc_pointers(ctx, &fninfo, true);
add_arg_checked(&fninfo, ARG_SGPR, ctx->f32,
SI_PARAM_ALPHA_REF);
add_arg_checked(&fninfo, ARG_SGPR, ctx->i32,
SI_PARAM_PRIM_MASK);
add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32,
SI_PARAM_PERSP_SAMPLE);
add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32,
SI_PARAM_PERSP_CENTER);
add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32,
SI_PARAM_PERSP_CENTROID);
add_arg_checked(&fninfo, ARG_VGPR, v3i32,
SI_PARAM_PERSP_PULL_MODEL);
add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32,
SI_PARAM_LINEAR_SAMPLE);
add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32,
SI_PARAM_LINEAR_CENTER);
add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32,
SI_PARAM_LINEAR_CENTROID);
@@ -4531,21 +4535,22 @@ static void create_function(struct si_shader_context
*ctx)
num_return_sgprs +
PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
for (i = 0; i < num_return_sgprs; i++)
returns[i] = ctx->i32;
for (; i < num_returns; i++)
returns[i] = ctx->f32;
break;
case PIPE_SHADER_COMPUTE:
- declare_default_desc_pointers(ctx, &fninfo);
+ declare_global_desc_pointers(ctx, &fninfo);
+ declare_per_stage_desc_pointers(ctx, &fninfo, true);
if (shader->selector->info.uses_grid_size)
ctx->param_grid_size = add_arg(&fninfo, ARG_SGPR,
v3i32);
if (shader->selector->info.uses_block_size)
ctx->param_block_size = add_arg(&fninfo, ARG_SGPR,
v3i32);
for (i = 0; i < 3; i++) {
ctx->param_block_id[i] = -1;
if (shader->selector->info.uses_block_id[i])
ctx->param_block_id[i] = add_arg(&fninfo,
ARG_SGPR, ctx->i32);
}
--
2.7.4
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