From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeon/r600_pipe_common.c | 99 +++------------------------
src/gallium/drivers/radeon/r600_pipe_common.h | 20 ------
src/gallium/drivers/radeon/r600_query.c | 31 +++------
src/gallium/drivers/radeon/r600_streamout.c | 96 ++++++--------------------
src/gallium/drivers/radeon/r600_texture.c | 4 --
src/gallium/drivers/radeon/radeon_uvd.c | 2 +-
src/gallium/drivers/radeon/radeon_video.c | 27 +++-----
7 files changed, 53 insertions(+), 226 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 495878b..fd4e2c1 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -97,21 +97,21 @@ void si_gfx_write_event_eop(struct r600_common_context *ctx,
uint32_t new_fence, unsigned query_type)
{
struct radeon_winsys_cs *cs = ctx->gfx.cs;
unsigned op = EVENT_TYPE(event) |
EVENT_INDEX(5) |
event_flags;
unsigned sel = EOP_DATA_SEL(data_sel);
/* Wait for write confirmation before writing data, but don't send
* an interrupt. */
- if (ctx->chip_class >= SI && data_sel != EOP_DATA_SEL_DISCARD)
+ if (data_sel != EOP_DATA_SEL_DISCARD)
sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
if (ctx->chip_class >= GFX9) {
/* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
* counters) must immediately precede every timestamp event to
* prevent a GPU hang on GFX9.
*
* Occlusion queries don't need to do it here, because they
* always do ZPASS_DONE before the timestamp.
*/
@@ -285,26 +285,22 @@ void si_draw_rectangle(struct blitter_context *blitter,
pipe_resource_reference(&buf, NULL);
}
static void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
{
struct radeon_winsys_cs *cs = rctx->dma.cs;
/* NOP waits for idle on Evergreen and later. */
if (rctx->chip_class >= CIK)
radeon_emit(cs, 0x00000000); /* NOP */
- else if (rctx->chip_class >= EVERGREEN)
+ else
radeon_emit(cs, 0xf0000000); /* NOP */
- else {
- /* TODO: R600-R700 should use the FENCE packet.
- * CS checker support is required. */
- }
}
void si_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
struct r600_resource *dst, struct r600_resource *src)
{
uint64_t vram = ctx->dma.cs->used_vram;
uint64_t gtt = ctx->dma.cs->used_gart;
if (dst) {
vram += dst->vram_usage;
@@ -891,45 +887,20 @@ static const char* r600_get_device_vendor(struct
pipe_screen* pscreen)
static const char *r600_get_marketing_name(struct radeon_winsys *ws)
{
if (!ws->get_chip_name)
return NULL;
return ws->get_chip_name(ws);
}
static const char *r600_get_family_name(const struct r600_common_screen
*rscreen)
{
switch (rscreen->info.family) {
- case CHIP_R600: return "AMD R600";
- case CHIP_RV610: return "AMD RV610";
- case CHIP_RV630: return "AMD RV630";
- case CHIP_RV670: return "AMD RV670";
- case CHIP_RV620: return "AMD RV620";
- case CHIP_RV635: return "AMD RV635";
- case CHIP_RS780: return "AMD RS780";
- case CHIP_RS880: return "AMD RS880";
- case CHIP_RV770: return "AMD RV770";
- case CHIP_RV730: return "AMD RV730";
- case CHIP_RV710: return "AMD RV710";
- case CHIP_RV740: return "AMD RV740";
- case CHIP_CEDAR: return "AMD CEDAR";
- case CHIP_REDWOOD: return "AMD REDWOOD";
- case CHIP_JUNIPER: return "AMD JUNIPER";
- case CHIP_CYPRESS: return "AMD CYPRESS";
- case CHIP_HEMLOCK: return "AMD HEMLOCK";
- case CHIP_PALM: return "AMD PALM";
- case CHIP_SUMO: return "AMD SUMO";
- case CHIP_SUMO2: return "AMD SUMO2";
- case CHIP_BARTS: return "AMD BARTS";
- case CHIP_TURKS: return "AMD TURKS";
- case CHIP_CAICOS: return "AMD CAICOS";
- case CHIP_CAYMAN: return "AMD CAYMAN";
- case CHIP_ARUBA: return "AMD ARUBA";
case CHIP_TAHITI: return "AMD TAHITI";
case CHIP_PITCAIRN: return "AMD PITCAIRN";
case CHIP_VERDE: return "AMD CAPE VERDE";
case CHIP_OLAND: return "AMD OLAND";
case CHIP_HAINAN: return "AMD HAINAN";
case CHIP_BONAIRE: return "AMD BONAIRE";
case CHIP_KAVERI: return "AMD KAVERI";
case CHIP_KABINI: return "AMD KABINI";
case CHIP_HAWAII: return "AMD HAWAII";
case CHIP_MULLINS: return "AMD MULLINS";
@@ -1042,60 +1013,20 @@ static int r600_get_video_param(struct pipe_screen
*screen,
case PIPE_VIDEO_CAP_MAX_LEVEL:
return vl_level_supported(screen, profile);
default:
return 0;
}
}
const char *si_get_llvm_processor_name(enum radeon_family family)
{
switch (family) {
- case CHIP_R600:
- case CHIP_RV630:
- case CHIP_RV635:
- case CHIP_RV670:
- return "r600";
- case CHIP_RV610:
- case CHIP_RV620:
- case CHIP_RS780:
- case CHIP_RS880:
- return "rs880";
- case CHIP_RV710:
- return "rv710";
- case CHIP_RV730:
- return "rv730";
- case CHIP_RV740:
- case CHIP_RV770:
- return "rv770";
- case CHIP_PALM:
- case CHIP_CEDAR:
- return "cedar";
- case CHIP_SUMO:
- case CHIP_SUMO2:
- return "sumo";
- case CHIP_REDWOOD:
- return "redwood";
- case CHIP_JUNIPER:
- return "juniper";
- case CHIP_HEMLOCK:
- case CHIP_CYPRESS:
- return "cypress";
- case CHIP_BARTS:
- return "barts";
- case CHIP_TURKS:
- return "turks";
- case CHIP_CAICOS:
- return "caicos";
- case CHIP_CAYMAN:
- case CHIP_ARUBA:
- return "cayman";
-
case CHIP_TAHITI: return "tahiti";
case CHIP_PITCAIRN: return "pitcairn";
case CHIP_VERDE: return "verde";
case CHIP_OLAND: return "oland";
case CHIP_HAINAN: return "hainan";
case CHIP_BONAIRE: return "bonaire";
case CHIP_KABINI: return "kabini";
case CHIP_KAVERI: return "kaveri";
case CHIP_HAWAII: return "hawaii";
case CHIP_MULLINS:
@@ -1141,37 +1072,27 @@ static int r600_get_compute_param(struct pipe_screen
*screen,
enum pipe_compute_cap param,
void *ret)
{
struct r600_common_screen *rscreen = (struct r600_common_screen
*)screen;
//TODO: select these params by asic
switch (param) {
case PIPE_COMPUTE_CAP_IR_TARGET: {
const char *gpu;
const char *triple;
- if (rscreen->family <= CHIP_ARUBA) {
- triple = "r600--";
- } else {
- if (HAVE_LLVM < 0x0400) {
- triple = "amdgcn--";
- } else {
- triple = "amdgcn-mesa-mesa3d";
- }
- }
- switch(rscreen->family) {
- /* Clang < 3.6 is missing Hainan in its list of
- * GPUs, so we need to use the name of a similar GPU.
- */
- default:
- gpu = si_get_llvm_processor_name(rscreen->family);
- break;
- }
+
+ if (HAVE_LLVM < 0x0400)
+ triple = "amdgcn--";
+ else
+ triple = "amdgcn-mesa-mesa3d";
+
+ gpu = si_get_llvm_processor_name(rscreen->family);
if (ret) {
sprintf(ret, "%s-%s", gpu, triple);
}
/* +2 for dash and terminating NIL byte */
return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
}
case PIPE_COMPUTE_CAP_GRID_DIMENSION:
if (ret) {
uint64_t *grid_dimension = ret;
grid_dimension[0] = 3;
@@ -1273,21 +1194,21 @@ static int r600_get_compute_param(struct pipe_screen
*screen,
if (ret) {
uint32_t *images_supported = ret;
*images_supported = 0;
}
return sizeof(uint32_t);
case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
break; /* unused */
case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
if (ret) {
uint32_t *subgroup_size = ret;
- *subgroup_size = r600_wavefront_size(rscreen->family);
+ *subgroup_size = 64;
}
return sizeof(uint32_t);
case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
if (ret) {
uint64_t *max_variable_threads_per_block = ret;
if (ir_type == PIPE_SHADER_IR_TGSI)
*max_variable_threads_per_block =
SI_MAX_VARIABLE_THREADS_PER_BLOCK;
else
*max_variable_threads_per_block = 0;
}
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 597ff02..074b321 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -920,40 +920,20 @@ static inline unsigned r600_tex_aniso_filter(unsigned
filter)
return 0;
if (filter < 4)
return 1;
if (filter < 8)
return 2;
if (filter < 16)
return 3;
return 4;
}
-static inline unsigned r600_wavefront_size(enum radeon_family family)
-{
- switch (family) {
- case CHIP_RV610:
- case CHIP_RS780:
- case CHIP_RV620:
- case CHIP_RS880:
- return 16;
- case CHIP_RV630:
- case CHIP_RV635:
- case CHIP_RV730:
- case CHIP_RV710:
- case CHIP_PALM:
- case CHIP_CEDAR:
- return 32;
- default:
- return 64;
- }
-}
-
static inline enum radeon_bo_priority
r600_get_sampler_view_priority(struct r600_resource *res)
{
if (res->b.b.target == PIPE_BUFFER)
return RADEON_PRIO_SAMPLER_BUFFER;
if (res->b.b.nr_samples > 1)
return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
return RADEON_PRIO_SAMPLER_TEXTURE;
diff --git a/src/gallium/drivers/radeon/r600_query.c
b/src/gallium/drivers/radeon/r600_query.c
index 9d850e9..f41cd8e 100644
--- a/src/gallium/drivers/radeon/r600_query.c
+++ b/src/gallium/drivers/radeon/r600_query.c
@@ -759,40 +759,31 @@ static void r600_query_hw_do_emit_start(struct
r600_common_context *ctx,
case PIPE_QUERY_PRIMITIVES_GENERATED:
case PIPE_QUERY_SO_STATISTICS:
case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
emit_sample_streamout(cs, va, query->stream);
break;
case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
for (unsigned stream = 0; stream < R600_MAX_STREAMS; ++stream)
emit_sample_streamout(cs, va + 32 * stream, stream);
break;
case PIPE_QUERY_TIME_ELAPSED:
- if (ctx->chip_class >= SI) {
- /* Write the timestamp from the CP not waiting for
- * outstanding draws (top-of-pipe).
- */
- radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
- radeon_emit(cs, COPY_DATA_COUNT_SEL |
- COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP) |
- COPY_DATA_DST_SEL(COPY_DATA_MEM_ASYNC));
- radeon_emit(cs, 0);
- radeon_emit(cs, 0);
- radeon_emit(cs, va);
- radeon_emit(cs, va >> 32);
- } else {
- /* Write the timestamp after the last draw is done.
- * (bottom-of-pipe)
- */
- si_gfx_write_event_eop(ctx,
EVENT_TYPE_BOTTOM_OF_PIPE_TS,
- 0, EOP_DATA_SEL_TIMESTAMP,
- NULL, va, 0, query->b.type);
- }
+ /* Write the timestamp from the CP not waiting for
+ * outstanding draws (top-of-pipe).
+ */
+ radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
+ radeon_emit(cs, COPY_DATA_COUNT_SEL |
+ COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP) |
+ COPY_DATA_DST_SEL(COPY_DATA_MEM_ASYNC));
+ radeon_emit(cs, 0);
+ radeon_emit(cs, 0);
+ radeon_emit(cs, va);
+ radeon_emit(cs, va >> 32);
break;
case PIPE_QUERY_PIPELINE_STATISTICS:
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) |
EVENT_INDEX(2));
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
break;
default:
assert(0);
}
diff --git a/src/gallium/drivers/radeon/r600_streamout.c
b/src/gallium/drivers/radeon/r600_streamout.c
index 40243e6..84f6035 100644
--- a/src/gallium/drivers/radeon/r600_streamout.c
+++ b/src/gallium/drivers/radeon/r600_streamout.c
@@ -82,34 +82,24 @@ void si_streamout_buffers_dirty(struct r600_common_context
*rctx)
rctx->streamout.append_bitmask);
if (!num_bufs)
return;
rctx->streamout.num_dw_for_end =
12 + /* flush_vgt_streamout */
num_bufs * 11; /* STRMOUT_BUFFER_UPDATE, BUFFER_SIZE */
begin->num_dw = 12; /* flush_vgt_streamout */
-
- if (rctx->chip_class >= SI) {
- begin->num_dw += num_bufs * 4; /* SET_CONTEXT_REG */
- } else {
- begin->num_dw += num_bufs * 7; /* SET_CONTEXT_REG */
-
- if (rctx->family >= CHIP_RS780 && rctx->family <= CHIP_RV740)
- begin->num_dw += num_bufs * 5; /* STRMOUT_BASE_UPDATE */
- }
-
+ begin->num_dw += num_bufs * 4; /* SET_CONTEXT_REG */
begin->num_dw +=
num_bufs_appended * 8 + /* STRMOUT_BUFFER_UPDATE */
- (num_bufs - num_bufs_appended) * 6 + /* STRMOUT_BUFFER_UPDATE */
- (rctx->family > CHIP_R600 && rctx->family < CHIP_RS780 ? 2 :
0); /* SURFACE_BASE_UPDATE */
+ (num_bufs - num_bufs_appended); + /* STRMOUT_BUFFER_UPDATE */
rctx->set_atom_dirty(rctx, begin, true);
r600_set_streamout_enable(rctx, true);
}
void si_common_set_streamout_targets(struct pipe_context *ctx,
unsigned num_targets,
struct pipe_stream_output_target **targets,
const unsigned *offsets)
@@ -152,92 +142,60 @@ void si_common_set_streamout_targets(struct pipe_context
*ctx,
}
static void r600_flush_vgt_streamout(struct r600_common_context *rctx)
{
struct radeon_winsys_cs *cs = rctx->gfx.cs;
unsigned reg_strmout_cntl;
/* The register is at different places on different ASICs. */
if (rctx->chip_class >= CIK) {
reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
- } else if (rctx->chip_class >= EVERGREEN) {
- reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
- } else {
- reg_strmout_cntl = R_008490_CP_STRMOUT_CNTL;
- }
-
- if (rctx->chip_class >= CIK) {
radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
} else {
+ reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
radeon_set_config_reg(cs, reg_strmout_cntl, 0);
}
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) |
EVENT_INDEX(0));
radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is
equal to the reference value */
radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
radeon_emit(cs, 0);
radeon_emit(cs, S_008490_OFFSET_UPDATE_DONE(1)); /* reference value */
radeon_emit(cs, S_008490_OFFSET_UPDATE_DONE(1)); /* mask */
radeon_emit(cs, 4); /* poll interval */
}
static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct
r600_atom *atom)
{
struct radeon_winsys_cs *cs = rctx->gfx.cs;
struct r600_so_target **t = rctx->streamout.targets;
uint16_t *stride_in_dw = rctx->streamout.stride_in_dw;
- unsigned i, update_flags = 0;
+ unsigned i;
r600_flush_vgt_streamout(rctx);
for (i = 0; i < rctx->streamout.num_targets; i++) {
if (!t[i])
continue;
t[i]->stride_in_dw = stride_in_dw[i];
- if (rctx->chip_class >= SI) {
- /* SI binds streamout buffers as shader resources.
- * VGT only counts primitives and tells the shader
- * through SGPRs what to do. */
- radeon_set_context_reg_seq(cs,
R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
- radeon_emit(cs, (t[i]->b.buffer_offset +
- t[i]->b.buffer_size) >> 2); /*
BUFFER_SIZE (in DW) */
- radeon_emit(cs, stride_in_dw[i]); /*
VTX_STRIDE (in DW) */
- } else {
- uint64_t va =
r600_resource(t[i]->b.buffer)->gpu_address;
-
- update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i);
-
- radeon_set_context_reg_seq(cs,
R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 3);
- radeon_emit(cs, (t[i]->b.buffer_offset +
- t[i]->b.buffer_size) >> 2); /*
BUFFER_SIZE (in DW) */
- radeon_emit(cs, stride_in_dw[i]); /*
VTX_STRIDE (in DW) */
- radeon_emit(cs, va >> 8); /*
BUFFER_BASE */
-
- r600_emit_reloc(rctx, &rctx->gfx,
r600_resource(t[i]->b.buffer),
- RADEON_USAGE_WRITE,
RADEON_PRIO_SHADER_RW_BUFFER);
-
- /* R7xx requires this packet after updating BUFFER_BASE.
- * Without this, R7xx locks up. */
- if (rctx->family >= CHIP_RS780 && rctx->family <=
CHIP_RV740) {
- radeon_emit(cs, PKT3(PKT3_STRMOUT_BASE_UPDATE,
1, 0));
- radeon_emit(cs, i);
- radeon_emit(cs, va >> 8);
-
- r600_emit_reloc(rctx, &rctx->gfx,
r600_resource(t[i]->b.buffer),
- RADEON_USAGE_WRITE,
RADEON_PRIO_SHADER_RW_BUFFER);
- }
- }
+ /* SI binds streamout buffers as shader resources.
+ * VGT only counts primitives and tells the shader
+ * through SGPRs what to do. */
+ radeon_set_context_reg_seq(cs,
R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
+ radeon_emit(cs, (t[i]->b.buffer_offset +
+ t[i]->b.buffer_size) >> 2); /* BUFFER_SIZE
(in DW) */
+ radeon_emit(cs, stride_in_dw[i]); /* VTX_STRIDE
(in DW) */
if (rctx->streamout.append_bitmask & (1 << i) &&
t[i]->buf_filled_size_valid) {
uint64_t va = t[i]->buf_filled_size->gpu_address +
t[i]->buf_filled_size_offset;
/* Append. */
radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
radeon_emit(cs, 0); /* unused */
@@ -252,24 +210,20 @@ static void r600_emit_streamout_begin(struct
r600_common_context *rctx, struct r
radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
radeon_emit(cs, 0); /* unused */
radeon_emit(cs, 0); /* unused */
radeon_emit(cs, t[i]->b.buffer_offset >> 2); /* buffer
offset in DW */
radeon_emit(cs, 0); /* unused */
}
}
- if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770) {
- radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
- radeon_emit(cs, update_flags);
- }
rctx->streamout.begin_emitted = true;
}
void si_emit_streamout_end(struct r600_common_context *rctx)
{
struct radeon_winsys_cs *cs = rctx->gfx.cs;
struct r600_so_target **t = rctx->streamout.targets;
unsigned i;
uint64_t va;
@@ -308,38 +262,30 @@ void si_emit_streamout_end(struct r600_common_context
*rctx)
/* STREAMOUT CONFIG DERIVED STATE
*
* Streamout must be enabled for the PRIMITIVES_GENERATED query to work.
* The buffer mask is an independent state, so no writes occur if there
* are no buffers bound.
*/
static void r600_emit_streamout_enable(struct r600_common_context *rctx,
struct r600_atom *atom)
{
- unsigned strmout_config_reg = R_028AB0_VGT_STRMOUT_EN;
- unsigned strmout_config_val =
S_028B94_STREAMOUT_0_EN(r600_get_strmout_en(rctx));
- unsigned strmout_buffer_reg = R_028B20_VGT_STRMOUT_BUFFER_EN;
- unsigned strmout_buffer_val = rctx->streamout.hw_enabled_mask &
-
rctx->streamout.enabled_stream_buffers_mask;
-
- if (rctx->chip_class >= EVERGREEN) {
- strmout_buffer_reg = R_028B98_VGT_STRMOUT_BUFFER_CONFIG;
-
- strmout_config_reg = R_028B94_VGT_STRMOUT_CONFIG;
- strmout_config_val |=
- S_028B94_RAST_STREAM(0) |
- S_028B94_STREAMOUT_1_EN(r600_get_strmout_en(rctx)) |
- S_028B94_STREAMOUT_2_EN(r600_get_strmout_en(rctx)) |
- S_028B94_STREAMOUT_3_EN(r600_get_strmout_en(rctx));
- }
- radeon_set_context_reg(rctx->gfx.cs, strmout_buffer_reg,
strmout_buffer_val);
- radeon_set_context_reg(rctx->gfx.cs, strmout_config_reg,
strmout_config_val);
+ radeon_set_context_reg_seq(rctx->gfx.cs, R_028B94_VGT_STRMOUT_CONFIG,
2);
+ radeon_emit(rctx->gfx.cs,
+ S_028B94_STREAMOUT_0_EN(r600_get_strmout_en(rctx)) |
+ S_028B94_RAST_STREAM(0) |
+ S_028B94_STREAMOUT_1_EN(r600_get_strmout_en(rctx)) |
+ S_028B94_STREAMOUT_2_EN(r600_get_strmout_en(rctx)) |
+ S_028B94_STREAMOUT_3_EN(r600_get_strmout_en(rctx)));
+ radeon_emit(rctx->gfx.cs,
+ rctx->streamout.hw_enabled_mask &
+ rctx->streamout.enabled_stream_buffers_mask);
}
static void r600_set_streamout_enable(struct r600_common_context *rctx, bool
enable)
{
bool old_strmout_en = r600_get_strmout_en(rctx);
unsigned old_hw_enabled_mask = rctx->streamout.hw_enabled_mask;
rctx->streamout.streamout_enabled = enable;
rctx->streamout.hw_enabled_mask = rctx->streamout.enabled_mask |
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index eb7560e..4167194 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -489,24 +489,20 @@ static void r600_reallocate_texture_inplace(struct
r600_common_context *rctx,
unsigned new_bind_flag,
bool invalidate_storage)
{
struct pipe_screen *screen = rctx->b.screen;
struct r600_texture *new_tex;
struct pipe_resource templ = rtex->resource.b.b;
unsigned i;
templ.bind |= new_bind_flag;
- /* r600g doesn't react to dirty_tex_descriptor_counter */
- if (rctx->chip_class < SI)
- return;
-
if (rtex->resource.b.is_shared)
return;
if (new_bind_flag == PIPE_BIND_LINEAR) {
if (rtex->surface.is_linear)
return;
/* This fails with MSAA, depth, and compressed textures. */
if (r600_choose_tiling(rctx->screen, &templ) !=
RADEON_SURF_MODE_LINEAR_ALIGNED)
diff --git a/src/gallium/drivers/radeon/radeon_uvd.c
b/src/gallium/drivers/radeon/radeon_uvd.c
index d381554..032ed7c 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
+++ b/src/gallium/drivers/radeon/radeon_uvd.c
@@ -1351,21 +1351,21 @@ struct pipe_video_codec
*si_common_uvd_create_decoder(struct pipe_context *conte
unsigned width = templ->width, height = templ->height;
unsigned bs_buf_size;
struct radeon_info info;
struct ruvd_decoder *dec;
int r, i;
ws->query_info(ws, &info);
switch(u_reduce_video_profile(templ->profile)) {
case PIPE_VIDEO_FORMAT_MPEG12:
- if (templ->entrypoint > PIPE_VIDEO_ENTRYPOINT_BITSTREAM ||
info.family < CHIP_PALM)
+ if (templ->entrypoint > PIPE_VIDEO_ENTRYPOINT_BITSTREAM)
return vl_create_mpeg12_decoder(context, templ);
/* fall through */
case PIPE_VIDEO_FORMAT_MPEG4:
width = align(width, VL_MACROBLOCK_WIDTH);
height = align(height, VL_MACROBLOCK_HEIGHT);
break;
case PIPE_VIDEO_FORMAT_MPEG4_AVC:
width = align(width, VL_MACROBLOCK_WIDTH);
height = align(height, VL_MACROBLOCK_HEIGHT);
diff --git a/src/gallium/drivers/radeon/radeon_video.c
b/src/gallium/drivers/radeon/radeon_video.c
index 08710fb..4f796e8 100644
--- a/src/gallium/drivers/radeon/radeon_video.c
+++ b/src/gallium/drivers/radeon/radeon_video.c
@@ -254,22 +254,21 @@ int si_vid_get_video_param(struct pipe_screen *screen,
return 0;
}
}
switch (param) {
case PIPE_VIDEO_CAP_SUPPORTED:
switch (codec) {
case PIPE_VIDEO_FORMAT_MPEG12:
return profile != PIPE_VIDEO_PROFILE_MPEG1;
case PIPE_VIDEO_FORMAT_MPEG4:
- /* no support for MPEG4 on older hw */
- return rscreen->family >= CHIP_PALM;
+ return 1;
case PIPE_VIDEO_FORMAT_MPEG4_AVC:
if ((rscreen->family == CHIP_POLARIS10 ||
rscreen->family == CHIP_POLARIS11) &&
info.uvd_fw_version < UVD_FW_1_66_16 ) {
RVID_ERR("POLARIS10/11 firmware version need to
be updated.\n");
return false;
}
return true;
case PIPE_VIDEO_FORMAT_VC1:
return true;
@@ -298,35 +297,29 @@ int si_vid_get_video_param(struct pipe_screen *screen,
return (rscreen->family < CHIP_TONGA) ? 2048 : 4096;
case PIPE_VIDEO_CAP_MAX_HEIGHT:
return (rscreen->family < CHIP_TONGA) ? 1152 : 4096;
case PIPE_VIDEO_CAP_PREFERED_FORMAT:
if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
return PIPE_FORMAT_P016;
else
return PIPE_FORMAT_NV12;
case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
- case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
- if (rscreen->family < CHIP_PALM) {
- /* MPEG2 only with shaders and no support for
- interlacing on R6xx style UVD */
- return codec != PIPE_VIDEO_FORMAT_MPEG12 &&
- rscreen->family > CHIP_RV770;
- } else {
- enum pipe_video_format format =
u_reduce_video_profile(profile);
-
- if (format == PIPE_VIDEO_FORMAT_HEVC)
- return false; //The firmware doesn't support
interlaced HEVC.
- else if (format == PIPE_VIDEO_FORMAT_JPEG)
- return false;
- return true;
- }
+ case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
+ enum pipe_video_format format = u_reduce_video_profile(profile);
+
+ if (format == PIPE_VIDEO_FORMAT_HEVC)
+ return false; //The firmware doesn't support interlaced
HEVC.
+ else if (format == PIPE_VIDEO_FORMAT_JPEG)
+ return false;
+ return true;
+ }
case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
return true;
case PIPE_VIDEO_CAP_MAX_LEVEL:
switch (profile) {
case PIPE_VIDEO_PROFILE_MPEG1:
return 0;
case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
return 3;
case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
--
2.7.4
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