From: Nicolai Hähnle <nicolai.haeh...@amd.com> --- src/gallium/auxiliary/gallivm/lp_bld_limits.h | 1 + src/gallium/auxiliary/tgsi/tgsi_exec.h | 1 + src/gallium/auxiliary/tgsi/tgsi_info_opcodes.h | 2 +- src/gallium/docs/source/screen.rst | 2 ++ src/gallium/docs/source/tgsi.rst | 18 ++++++++++++++++++ src/gallium/drivers/etnaviv/etnaviv_screen.c | 1 + src/gallium/drivers/freedreno/freedreno_screen.c | 1 + src/gallium/drivers/nouveau/nv30/nv30_screen.c | 2 ++ src/gallium/drivers/nouveau/nv50/nv50_screen.c | 1 + src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 1 + src/gallium/drivers/r300/r300_screen.c | 2 ++ src/gallium/drivers/r600/r600_pipe.c | 1 + src/gallium/drivers/radeonsi/si_pipe.c | 1 + src/gallium/drivers/svga/svga_screen.c | 3 +++ src/gallium/drivers/vc4/vc4_screen.c | 1 + src/gallium/drivers/virgl/virgl_screen.c | 1 + src/gallium/include/pipe/p_defines.h | 1 + src/gallium/include/pipe/p_shader_tokens.h | 2 +- 18 files changed, 40 insertions(+), 2 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_limits.h b/src/gallium/auxiliary/gallivm/lp_bld_limits.h index 66ecd4b8f2a..9f1fb5c4482 100644 --- a/src/gallium/auxiliary/gallivm/lp_bld_limits.h +++ b/src/gallium/auxiliary/gallivm/lp_bld_limits.h @@ -130,20 +130,21 @@ gallivm_get_shader_param(enum pipe_shader_cap param) case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: return 1; case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: + case PIPE_SHADER_CAP_TGSI_CANON: return 0; case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: return 32; } /* if we get here, we missed a shader cap above (and should have seen * a compiler warning.) */ return 0; } diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.h b/src/gallium/auxiliary/tgsi/tgsi_exec.h index f252b86195e..103a92a7aab 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_exec.h +++ b/src/gallium/auxiliary/tgsi/tgsi_exec.h @@ -531,20 +531,21 @@ tgsi_exec_get_shader_param(enum pipe_shader_cap param) case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: return 1; case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: return 1; case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: + case PIPE_SHADER_CAP_TGSI_CANON: return 0; case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: return PIPE_MAX_SHADER_BUFFERS; case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: return PIPE_MAX_SHADER_IMAGES; case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: return 32; } /* if we get here, we missed a shader cap above (and should have seen diff --git a/src/gallium/auxiliary/tgsi/tgsi_info_opcodes.h b/src/gallium/auxiliary/tgsi/tgsi_info_opcodes.h index fdb0f1078a1..3bf6acca608 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_info_opcodes.h +++ b/src/gallium/auxiliary/tgsi/tgsi_info_opcodes.h @@ -22,21 +22,21 @@ OPCODE(1, 1, REPL, SQRT) OPCODE(1, 2, COMP, LDEXP) OPCODE(1, 1, COMP, F2U64) OPCODE(1, 1, COMP, F2I64) OPCODE(1, 1, COMP, FRC) OPCODE(1, 2, OTHR, TXF_LZ, .is_tex = 1) OPCODE(1, 1, COMP, FLR) OPCODE(1, 1, COMP, ROUND) OPCODE(1, 1, REPL, EX2) OPCODE(1, 1, REPL, LG2) OPCODE(1, 2, REPL, POW) -OPCODE_GAP(31) /* removed */ +OPCODE(1, 1, COMP, CANON) OPCODE(1, 1, COMP, U2I64) OPCODE(1, 0, OTHR, CLOCK) OPCODE(1, 1, COMP, I2I64) OPCODE_GAP(35) /* removed */ OPCODE(1, 1, REPL, COS) OPCODE(1, 1, COMP, DDX) OPCODE(1, 1, COMP, DDY) OPCODE(0, 0, NONE, KILL) OPCODE(1, 1, REPL, PK2H) OPCODE(1, 1, REPL, PK2US) diff --git a/src/gallium/docs/source/screen.rst b/src/gallium/docs/source/screen.rst index af17db6739d..db2eb8bd0f6 100644 --- a/src/gallium/docs/source/screen.rst +++ b/src/gallium/docs/source/screen.rst @@ -496,20 +496,22 @@ MOV OUT[0], CONST[0][3] # copy vector 3 of constbuf 0 * ``PIPE_SHADER_CAP_SUPPORTED_IRS``: Supported representations of the program. It should be a mask of ``pipe_shader_ir`` bits. * ``PIPE_SHADER_CAP_MAX_SHADER_IMAGES``: Maximum number of image units. * ``PIPE_SHADER_CAP_LOWER_IF_THRESHOLD``: IF and ELSE branches with a lower cost than this value should be lowered by the state tracker for better performance. This is a tunable for the GLSL compiler and the behavior is specific to the compiler. * ``PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS``: Whether the merge registers TGSI pass is skipped. This might reduce code size and register pressure if the underlying driver has a real backend compiler. +* ``PIPE_SHADER_CAP_TGSI_CANON``: Whether CANON instructions should be + inserted by frontends. .. _pipe_compute_cap: PIPE_COMPUTE_CAP_* ^^^^^^^^^^^^^^^^^^ Compute-specific capabilities. They can be queried using pipe_screen::get_compute_param. diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst index 274646703b4..8a281ac9d75 100644 --- a/src/gallium/docs/source/tgsi.rst +++ b/src/gallium/docs/source/tgsi.rst @@ -1565,20 +1565,38 @@ These opcodes are used for bit-level manipulation of integers. See SM5 instruction FIRSTBIT_SHI. Computes the 0-based index of the highest non-sign bit of the argument (i.e. highest 0 bit for negative numbers, highest 1 bit for positive numbers). Returns -1 if all bits are the same (i.e. for inputs 0 and -1). .. opcode:: UMSB - Index of highest set bit See SM5 instruction FIRSTBIT_HI. Computes the 0-based index of the highest set bit of the argument. Returns -1 if none are set. + +.. opcode:: CANON - Canonicalize 32-bit floating point number + + Ensure that a floating point number is in its canonical bitwise + representation. For example, an implementation without denormals in which + denormals are not always flushed to zero in opcodes such as MIN/MAX may + explicitly flush denormals to zero with this instruction. A typical + implementation would be multiplication by 1.0 (but with different rules for + when this multiplication can be optimized away). + +.. math:: + + dst.x = canonicalize(src.x) + dst.y = canonicalize(src.y) + dst.z = canonicalize(src.z) + dst.w = canonicalize(src.w) + + Geometry ISA ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ These opcodes are only supported in geometry shaders; they have no meaning in any other type of shader. .. opcode:: EMIT - Emit Generate a new vertex for the current primitive into the specified vertex stream using the values in the output registers. diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c b/src/gallium/drivers/etnaviv/etnaviv_screen.c index 54d43d1c3d9..cd31c52e35a 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_screen.c +++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c @@ -444,20 +444,21 @@ etna_screen_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: return false; case PIPE_SHADER_CAP_SUPPORTED_IRS: return 0; case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: return 32; case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: + case PIPE_SHADER_CAP_TGSI_CANON: return 0; } debug_printf("unknown shader param %d", param); return 0; } static uint64_t etna_screen_get_timestamp(struct pipe_screen *pscreen) { diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c index 18eee7955f9..df5b9387f92 100644 --- a/src/gallium/drivers/freedreno/freedreno_screen.c +++ b/src/gallium/drivers/freedreno/freedreno_screen.c @@ -538,20 +538,21 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen, if (is_ir3(screen)) { return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI); } else { return (1 << PIPE_SHADER_IR_TGSI); } return 0; case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: return 32; case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: + case PIPE_SHADER_CAP_TGSI_CANON: return 0; case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: if (is_a5xx(screen)) { /* a5xx (and a4xx for that matter) has one state-block * for compute-shader SSBO's and another that is shared * by VS/HS/DS/GS/FS.. so to simplify things for now * just advertise SSBOs for FS and CS. We could possibly * do what blob does, and partition the space for * VS/HS/DS/GS/FS. The blob advertises: * diff --git a/src/gallium/drivers/nouveau/nv30/nv30_screen.c b/src/gallium/drivers/nouveau/nv30/nv30_screen.c index e4e2d4d4052..6036da6c6ca 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_screen.c +++ b/src/gallium/drivers/nouveau/nv30/nv30_screen.c @@ -315,20 +315,21 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_INTEGERS: case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: + case PIPE_SHADER_CAP_TGSI_CANON: return 0; default: debug_printf("unknown vertex shader param %d\n", param); return 0; } break; case PIPE_SHADER_FRAGMENT: switch (param) { case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: @@ -364,20 +365,21 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_INTEGERS: case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: + case PIPE_SHADER_CAP_TGSI_CANON: return 0; default: debug_printf("unknown fragment shader param %d\n", param); return 0; } break; default: return 0; } } diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c b/src/gallium/drivers/nouveau/nv50/nv50_screen.c index 3873f866d5c..fcce95b02c2 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c @@ -360,20 +360,21 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen, return 32; case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: case PIPE_SHADER_CAP_SUPPORTED_IRS: case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: + case PIPE_SHADER_CAP_TGSI_CANON: return 0; default: NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param); return 0; } } static float nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param) { diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c index da9ee0ff91f..b791a9335ad 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c @@ -398,20 +398,21 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: return 1; case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: return 1; case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: return 1; case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: + case PIPE_SHADER_CAP_TGSI_CANON: return 0; case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: return NVC0_MAX_BUFFERS; case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: return (class_3d >= NVE4_3D_CLASS) ? 32 : 16; case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: return (class_3d >= NVE4_3D_CLASS) ? 32 : 16; case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: return 32; case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index 48fcf57d0fa..b02a9d6726b 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -354,20 +354,21 @@ static int r300_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_SUBROUTINES: case PIPE_SHADER_CAP_INTEGERS: case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: + case PIPE_SHADER_CAP_TGSI_CANON: return 0; case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: return 32; case PIPE_SHADER_CAP_PREFERRED_IR: return PIPE_SHADER_IR_TGSI; case PIPE_SHADER_CAP_SUPPORTED_IRS: return 0; } break; case PIPE_SHADER_VERTEX: @@ -416,20 +417,21 @@ static int r300_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: + case PIPE_SHADER_CAP_TGSI_CANON: return 0; case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: return 32; case PIPE_SHADER_CAP_PREFERRED_IR: return PIPE_SHADER_IR_TGSI; case PIPE_SHADER_CAP_SUPPORTED_IRS: return 0; } break; default: diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c index 943bf16e052..75f10b71633 100644 --- a/src/gallium/drivers/r600/r600_pipe.c +++ b/src/gallium/drivers/r600/r600_pipe.c @@ -591,20 +591,21 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, rscreen->b.family == CHIP_HEMLOCK) return 1; return 0; case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED: case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: + case PIPE_SHADER_CAP_TGSI_CANON: return 0; case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: /* due to a bug in the shader compiler, some loops hang * if they are not unrolled, see: * https://bugs.freedesktop.org/show_bug.cgi?id=86720 */ return 255; } return 0; } diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 531e6148553..d310396680b 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -759,20 +759,21 @@ static int si_get_shader_param(struct pipe_screen* pscreen, shader == PIPE_SHADER_TESS_EVAL); case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: return sscreen->llvm_has_working_vgpr_indexing || /* TCS stores outputs directly to memory. */ shader == PIPE_SHADER_TESS_CTRL; /* Unsupported boolean features. */ case PIPE_SHADER_CAP_SUBROUTINES: case PIPE_SHADER_CAP_SUPPORTED_IRS: + case PIPE_SHADER_CAP_TGSI_CANON: return 0; } return 0; } static const struct nir_shader_compiler_options nir_options = { .vertex_id_zero_based = true, .lower_scmp = true, .lower_flrp32 = true, .lower_fsat = true, diff --git a/src/gallium/drivers/svga/svga_screen.c b/src/gallium/drivers/svga/svga_screen.c index d053614e352..c540c9ea7c3 100644 --- a/src/gallium/drivers/svga/svga_screen.c +++ b/src/gallium/drivers/svga/svga_screen.c @@ -527,20 +527,21 @@ vgpu9_get_shader_param(struct pipe_screen *screen, return 0; case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: + case PIPE_SHADER_CAP_TGSI_CANON: return 0; case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: return 32; } /* If we get here, we failed to handle a cap above */ debug_printf("Unexpected fragment shader query %u\n", param); return 0; case PIPE_SHADER_VERTEX: switch (param) { @@ -589,20 +590,21 @@ vgpu9_get_shader_param(struct pipe_screen *screen, return 0; case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: + case PIPE_SHADER_CAP_TGSI_CANON: return 0; case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: return 32; } /* If we get here, we failed to handle a cap above */ debug_printf("Unexpected vertex shader query %u\n", param); return 0; case PIPE_SHADER_GEOMETRY: case PIPE_SHADER_COMPUTE: case PIPE_SHADER_TESS_CTRL: @@ -685,20 +687,21 @@ vgpu10_get_shader_param(struct pipe_screen *screen, return 0; case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: + case PIPE_SHADER_CAP_TGSI_CANON: return 0; case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: return 32; default: debug_printf("Unexpected vgpu10 shader query %u\n", param); return 0; } return 0; } diff --git a/src/gallium/drivers/vc4/vc4_screen.c b/src/gallium/drivers/vc4/vc4_screen.c index 940c720885f..a77ab40cd47 100644 --- a/src/gallium/drivers/vc4/vc4_screen.c +++ b/src/gallium/drivers/vc4/vc4_screen.c @@ -418,20 +418,21 @@ vc4_screen_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_PREFERRED_IR: return PIPE_SHADER_IR_NIR; case PIPE_SHADER_CAP_SUPPORTED_IRS: return 0; case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: return 32; case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: + case PIPE_SHADER_CAP_TGSI_CANON: return 0; default: fprintf(stderr, "unknown shader param %d\n", param); return 0; } return 0; } static boolean vc4_screen_is_format_supported(struct pipe_screen *pscreen, diff --git a/src/gallium/drivers/virgl/virgl_screen.c b/src/gallium/drivers/virgl/virgl_screen.c index 68d74adadda..f4b1e0d6b46 100644 --- a/src/gallium/drivers/virgl/virgl_screen.c +++ b/src/gallium/drivers/virgl/virgl_screen.c @@ -327,20 +327,21 @@ virgl_get_shader_param(struct pipe_screen *screen, case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: return 16; case PIPE_SHADER_CAP_INTEGERS: return vscreen->caps.caps.v1.glsl_level >= 130; case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: return 32; case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: return 4096 * sizeof(float[4]); case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: + case PIPE_SHADER_CAP_TGSI_CANON: default: return 0; } default: return 0; } } static float virgl_get_paramf(struct pipe_screen *screen, enum pipe_capf param) diff --git a/src/gallium/include/pipe/p_defines.h b/src/gallium/include/pipe/p_defines.h index 4485c7b3bfd..4ca9b42a627 100644 --- a/src/gallium/include/pipe/p_defines.h +++ b/src/gallium/include/pipe/p_defines.h @@ -838,20 +838,21 @@ enum pipe_shader_cap PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED, PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED, PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE, PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT, PIPE_SHADER_CAP_MAX_SHADER_BUFFERS, PIPE_SHADER_CAP_SUPPORTED_IRS, PIPE_SHADER_CAP_MAX_SHADER_IMAGES, PIPE_SHADER_CAP_LOWER_IF_THRESHOLD, PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS, PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED, + PIPE_SHADER_CAP_TGSI_CANON, }; /** * Shader intermediate representation. * * Note that if the driver requests something other than TGSI, it must * always be prepared to receive TGSI in addition to its preferred IR. * If the driver requests TGSI as its preferred IR, it will *always* * get TGSI. * diff --git a/src/gallium/include/pipe/p_shader_tokens.h b/src/gallium/include/pipe/p_shader_tokens.h index a1fdf8cc24e..3f5487a47e1 100644 --- a/src/gallium/include/pipe/p_shader_tokens.h +++ b/src/gallium/include/pipe/p_shader_tokens.h @@ -361,21 +361,21 @@ struct tgsi_property_data { #define TGSI_OPCODE_LDEXP 21 #define TGSI_OPCODE_F2U64 22 #define TGSI_OPCODE_F2I64 23 #define TGSI_OPCODE_FRC 24 #define TGSI_OPCODE_TXF_LZ 25 #define TGSI_OPCODE_FLR 26 #define TGSI_OPCODE_ROUND 27 #define TGSI_OPCODE_EX2 28 #define TGSI_OPCODE_LG2 29 #define TGSI_OPCODE_POW 30 -/* gap */ +#define TGSI_OPCODE_CANON 31 #define TGSI_OPCODE_U2I64 32 #define TGSI_OPCODE_CLOCK 33 #define TGSI_OPCODE_I2I64 34 /* gap */ #define TGSI_OPCODE_COS 36 #define TGSI_OPCODE_DDX 37 #define TGSI_OPCODE_DDY 38 #define TGSI_OPCODE_KILL 39 /* unconditional */ #define TGSI_OPCODE_PK2H 40 #define TGSI_OPCODE_PK2US 41 -- 2.11.0 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev