---
src/mesa/drivers/dri/i965/gen7_wm_state.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index a994836..6a45520 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -144,6 +144,7 @@ upload_ps_state(struct brw_context *brw)
dw2 = dw4 = dw5 = 0;
+ /* CACHE_NEW_SAMPLER */
dw2 |= (ALIGN(brw->sampler.count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
/* Use ALT floating point mode for ARB fragment programs, because they
@@ -152,7 +153,6 @@ upload_ps_state(struct brw_context *brw)
if (intel->ctx.Shader.CurrentFragmentProgram == NULL)
dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
- /* CACHE_NEW_SAMPLER */
dw4 |= (brw->max_wm_threads - 1) << GEN7_PS_MAX_THREADS_SHIFT;
/* CACHE_NEW_WM_PROG */
--
1.7.7.3
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