This will reduce fragility in the implementation of
VK_ANDROID_native_buffer, which must do the equivalent of
vkAllocateMemory inside of vkCreateImage.
No behavioral change.
---
src/intel/vulkan/anv_blorp.c | 12 ++++++------
src/intel/vulkan/anv_image.c | 12 ++++++------
src/intel/vulkan/anv_intel.c | 4 ++--
src/intel/vulkan/anv_private.h | 4 ++--
src/intel/vulkan/anv_wsi.c | 2 +-
src/intel/vulkan/genX_cmd_buffer.c | 34 +++++++++++++++++-----------------
6 files changed, 34 insertions(+), 34 deletions(-)
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 915643ffa3c..cf1888ca472 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -191,16 +191,16 @@ get_blorp_surf_for_anv_image(const struct anv_image
*image,
*blorp_surf = (struct blorp_surf) {
.surf = &surface->isl,
.addr = {
- .buffer = image->bo,
- .offset = image->offset + surface->offset,
+ .buffer = image->mem->bo,
+ .offset = image->mem_offset + surface->offset,
},
};
if (aux_usage != ISL_AUX_USAGE_NONE) {
blorp_surf->aux_surf = &image->aux_surface.isl,
blorp_surf->aux_addr = (struct blorp_address) {
- .buffer = image->bo,
- .offset = image->offset + image->aux_surface.offset,
+ .buffer = image->mem->bo,
+ .offset = image->mem_offset + image->aux_surface.offset,
};
blorp_surf->aux_usage = aux_usage;
}
@@ -1515,8 +1515,8 @@ anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
/* Manually add the aux HiZ surf */
surf.aux_surf = &image->aux_surface.isl,
surf.aux_addr = (struct blorp_address) {
- .buffer = image->bo,
- .offset = image->offset + image->aux_surface.offset,
+ .buffer = image->mem->bo,
+ .offset = image->mem_offset + image->aux_surface.offset,
};
surf.aux_usage = ISL_AUX_USAGE_HIZ;
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index c38cd5f3e79..1fe8ab8ee43 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -493,13 +493,13 @@ VkResult anv_BindImageMemory(
ANV_FROM_HANDLE(anv_image, image, _image);
if (mem == NULL) {
- image->bo = NULL;
- image->offset = 0;
+ image->mem = NULL;
+ image->mem_offset = 0;
return VK_SUCCESS;
}
- image->bo = mem->bo;
- image->offset = memoryOffset;
+ image->mem = mem;
+ image->mem_offset = memoryOffset;
return VK_SUCCESS;
}
@@ -757,8 +757,8 @@ anv_CreateImageView(VkDevice _device,
anv_image_get_surface_for_aspect_mask(image, range->aspectMask);
iview->image = image;
- iview->bo = image->bo;
- iview->offset = image->offset + surface->offset;
+ iview->bo = image->mem->bo;
+ iview->offset = image->mem_offset + surface->offset;
iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
iview->vk_format = pCreateInfo->format;
diff --git a/src/intel/vulkan/anv_intel.c b/src/intel/vulkan/anv_intel.c
index 991a93542d2..172ae1dabf2 100644
--- a/src/intel/vulkan/anv_intel.c
+++ b/src/intel/vulkan/anv_intel.c
@@ -80,8 +80,8 @@ VkResult anv_CreateDmaBufImageINTEL(
pAllocator, &image_h);
image = anv_image_from_handle(image_h);
- image->bo = mem->bo;
- image->offset = 0;
+ image->mem = mem;
+ image->mem_offset = 0;
assert(image->extent.width > 0);
assert(image->extent.height > 0);
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 8020a5ab0d3..98bdaa90a50 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -2086,8 +2086,8 @@ struct anv_image {
uint32_t alignment;
/* Set when bound */
- struct anv_bo *bo;
- VkDeviceSize offset;
+ struct anv_device_memory *mem;
+ VkDeviceSize mem_offset;
/**
* Image subsurfaces
diff --git a/src/intel/vulkan/anv_wsi.c b/src/intel/vulkan/anv_wsi.c
index 00edb220b2b..26a85c99447 100644
--- a/src/intel/vulkan/anv_wsi.c
+++ b/src/intel/vulkan/anv_wsi.c
@@ -265,7 +265,7 @@ anv_wsi_image_create(VkDevice device_h,
*memory_p = memory_h;
*fd_p = fd;
*size = image->size;
- *offset = image->offset;
+ *offset = image->mem_offset;
return VK_SUCCESS;
fail_alloc_memory:
anv_FreeMemory(device_h, memory_h, pAllocator);
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index 7d7c5fbf9b1..5d97dbe8eb2 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -186,13 +186,13 @@ add_image_relocs(struct anv_cmd_buffer * const cmd_buffer,
const struct anv_state state)
{
const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
- const uint32_t surf_offset = image->offset +
+ const uint32_t surf_offset = image->mem_offset +
anv_image_get_surface_for_aspect_mask(image, aspect_mask)->offset;
- add_surface_state_reloc(cmd_buffer, state, image->bo, surf_offset);
+ add_surface_state_reloc(cmd_buffer, state, image->mem->bo, surf_offset);
if (aux_usage != ISL_AUX_USAGE_NONE) {
- uint32_t aux_offset = image->offset + image->aux_surface.offset;
+ uint32_t aux_offset = image->mem_offset + image->aux_surface.offset;
/* On gen7 and prior, the bottom 12 bits of the MCS base address are
* used to store other information. This should be ok, however, because
@@ -206,7 +206,7 @@ add_image_relocs(struct anv_cmd_buffer * const cmd_buffer,
anv_reloc_list_add(&cmd_buffer->surface_relocs,
&cmd_buffer->pool->alloc,
state.offset + isl_dev->ss.aux_addr_offset,
- image->bo, aux_offset);
+ image->mem->bo, aux_offset);
if (result != VK_SUCCESS)
anv_batch_set_error(&cmd_buffer->batch, result);
}
@@ -420,7 +420,7 @@ get_fast_clear_state_offset(const struct anv_device *device,
assert(device && image);
assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
assert(level < anv_image_aux_levels(image));
- uint32_t offset = image->offset + image->aux_surface.offset +
+ uint32_t offset = image->mem_offset + image->aux_surface.offset +
image->aux_surface.isl.size +
anv_fast_clear_state_entry_size(device) * level;
@@ -432,7 +432,7 @@ get_fast_clear_state_offset(const struct anv_device *device,
break;
}
- assert(offset < image->offset + image->size);
+ assert(offset < image->mem_offset + image->size);
return offset;
}
@@ -460,7 +460,7 @@ genX(set_image_needs_resolve)(struct anv_cmd_buffer
*cmd_buffer,
* issues in testing is currently being used in the GL driver.
*/
anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
- sdi.Address = (struct anv_address) { image->bo, resolve_flag_offset };
+ sdi.Address = (struct anv_address) { image->mem->bo, resolve_flag_offset
};
sdi.ImmediateData = needs_resolve;
}
}
@@ -485,7 +485,7 @@ genX(load_needs_resolve_predicate)(struct anv_cmd_buffer
*cmd_buffer,
emit_lri(&cmd_buffer->batch, MI_PREDICATE_SRC1 + 4, 0);
emit_lri(&cmd_buffer->batch, MI_PREDICATE_SRC0 , 0);
emit_lrm(&cmd_buffer->batch, MI_PREDICATE_SRC0 + 4,
- image->bo, resolve_flag_offset);
+ image->mem->bo, resolve_flag_offset);
anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
mip.LoadOperation = LOAD_LOADINV;
mip.CombineOperation = COMBINE_SET;
@@ -528,7 +528,7 @@ init_fast_clear_state_entry(struct anv_cmd_buffer
*cmd_buffer,
const uint32_t entry_offset =
get_fast_clear_state_offset(cmd_buffer->device, image, level,
FAST_CLEAR_STATE_FIELD_CLEAR_COLOR);
- sdi.Address = (struct anv_address) { image->bo, entry_offset + i };
+ sdi.Address = (struct anv_address) { image->mem->bo, entry_offset + i
};
if (GEN_GEN >= 9) {
/* MCS buffers on SKL+ can only have 1/0 clear colors. */
@@ -579,11 +579,11 @@ genX(copy_fast_clear_dwords)(struct anv_cmd_buffer
*cmd_buffer,
unsigned copy_size = cmd_buffer->device->isl_dev.ss.clear_value_size;
if (copy_from_surface_state) {
- genX(cmd_buffer_mi_memcpy)(cmd_buffer, image->bo, entry_offset,
+ genX(cmd_buffer_mi_memcpy)(cmd_buffer, image->mem->bo, entry_offset,
ss_bo, ss_clear_offset, copy_size);
} else {
genX(cmd_buffer_mi_memcpy)(cmd_buffer, ss_bo, ss_clear_offset,
- image->bo, entry_offset, copy_size);
+ image->mem->bo, entry_offset, copy_size);
/* Updating a surface state object may require that the state cache be
* invalidated. From the SKL PRM, Shared Functions -> State -> State
@@ -2765,8 +2765,8 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer)
info.depth_address =
anv_batch_emit_reloc(&cmd_buffer->batch,
dw + device->isl_dev.ds.depth_offset / 4,
- image->bo,
- image->offset + image->depth_surface.offset);
+ image->mem->bo,
+ image->mem_offset + image->depth_surface.offset);
const uint32_t ds =
cmd_buffer->state.subpass->depth_stencil_attachment.attachment;
@@ -2777,8 +2777,8 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer)
info.hiz_address =
anv_batch_emit_reloc(&cmd_buffer->batch,
dw + device->isl_dev.ds.hiz_offset / 4,
- image->bo,
- image->offset + image->aux_surface.offset);
+ image->mem->bo,
+ image->mem_offset +
image->aux_surface.offset);
info.depth_clear_value = ANV_HZ_FC_VAL;
}
@@ -2790,8 +2790,8 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer)
info.stencil_address =
anv_batch_emit_reloc(&cmd_buffer->batch,
dw + device->isl_dev.ds.stencil_offset / 4,
- image->bo,
- image->offset + image->stencil_surface.offset);
+ image->mem->bo,
+ image->mem_offset +
image->stencil_surface.offset);
}
isl_emit_depth_stencil_hiz_s(&device->isl_dev, dw, &info);
--
2.13.5
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