From: Jose Maria Casanova Crespo <jmcasan...@igalia.com>
The VS load input for 16-bit values receives pairs of 16-bit values
packed in 32-bit values. Because of the adjusted format used at:
anv/pipeline: Use 32-bit surface formats for 16-bit formats
---
src/intel/compiler/brw_fs_nir.cpp | 29 +++++++++++++++++++++++++++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index 6773615d1e3..be30c141f2b 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -2351,8 +2351,33 @@ fs_visitor::nir_emit_vs_intrinsic(const fs_builder &bld,
assert(const_offset && "Indirect input loads not allowed");
src = offset(src, bld, const_offset->u32[0]);
- for (unsigned j = 0; j < num_components; j++) {
- bld.MOV(offset(dest, bld, j), offset(src, bld, j + first_component));
+ /* The VS load input for 16-bit values receives pairs of 16-bit values
+ * packed in 32-bit values. This is an example on SIMD8:
+ *
+ * xy xy xy xy xy xy xy xy
+ * zw zw zw zw yw zw zw xw
+ *
+ * We need to format it to something like:
+ *
+ * xx xx xx xx yy yy yy yy
+ * zz zz zz zz ww ww ww ww
+ *
+ * As we are setting an stride = 2 by default. We finally receive:
+ *
+ * x0 x0 x0 x0 x0 x0 x0 x0
+ * y0 y0 y0 y0 y0 y0 y0 y0
+ * z0 z0 z0 z0 z0 z0 z0 z0
+ * w0 w0 w0 w0 w0 w0 w0 w0
+ */
+ if (type_sz(type) == 2) {
+ dest.stride = 2;
+ for (unsigned j = 0; j < num_components; j++)
+ bld.MOV(offset(dest, bld, j),
+ subscript(retype(offset(src,bld, (j / 2) * 2 +
first_component),
+ BRW_REGISTER_TYPE_F), type, j % 2));
+ } else {
+ for (unsigned j = 0; j < num_components; j++)
+ bld.MOV(offset(dest, bld, j), offset(src, bld, j +
first_component));
}
if (type == BRW_REGISTER_TYPE_DF) {
--
2.11.0
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