From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeonsi/si_state.c | 41 ++++++++++++++++++---------------
1 file changed, 22 insertions(+), 19 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index ab0bb57..4772df2 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -4267,20 +4267,39 @@ static void si_apply_opaque_metadata(struct
r600_common_screen *rscreen,
rtex->dcc_offset = 0;
}
void si_init_screen_state_functions(struct si_screen *sscreen)
{
sscreen->b.b.is_format_supported = si_is_format_supported;
sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
}
+static void si_set_grbm_gfx_index(struct si_context *sctx,
+ struct si_pm4_state *pm4, unsigned value)
+{
+ unsigned reg = sctx->b.chip_class >= CIK ? R_030800_GRBM_GFX_INDEX :
+ GRBM_GFX_INDEX;
+ si_pm4_set_reg(pm4, reg, value);
+}
+
+static void si_set_grbm_gfx_index_se(struct si_context *sctx,
+ struct si_pm4_state *pm4, unsigned se)
+{
+ assert(se == ~0 || se < sctx->screen->b.info.max_se);
+ si_set_grbm_gfx_index(sctx, pm4,
+ (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
+ S_030800_SE_INDEX(se)) |
+ S_030800_SH_BROADCAST_WRITES(1) |
+ S_030800_INSTANCE_BROADCAST_WRITES(1));
+}
+
static void
si_write_harvested_raster_configs(struct si_context *sctx,
struct si_pm4_state *pm4,
unsigned raster_config,
unsigned raster_config_1)
{
unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
@@ -4369,42 +4388,26 @@ si_write_harvested_raster_configs(struct si_context
*sctx,
raster_config_se |=
S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
} else {
raster_config_se |=
S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
}
}
}
}
- /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
- if (sctx->b.chip_class < CIK)
- si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
- SE_INDEX(se) | SH_BROADCAST_WRITES |
- INSTANCE_BROADCAST_WRITES);
- else
- si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
- S_030800_SE_INDEX(se) |
S_030800_SH_BROADCAST_WRITES(1) |
- S_030800_INSTANCE_BROADCAST_WRITES(1));
+ si_set_grbm_gfx_index_se(sctx, pm4, se);
si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
raster_config_se);
}
+ si_set_grbm_gfx_index(sctx, pm4, ~0);
- /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
- if (sctx->b.chip_class < CIK)
- si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
- SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
- INSTANCE_BROADCAST_WRITES);
- else {
- si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
- S_030800_SE_BROADCAST_WRITES(1) |
S_030800_SH_BROADCAST_WRITES(1) |
- S_030800_INSTANCE_BROADCAST_WRITES(1));
-
+ if (sctx->b.chip_class >= CIK) {
if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
(!se_mask[2] && !se_mask[3]))) {
raster_config_1 &= C_028354_SE_PAIR_MAP;
if (!se_mask[0] && !se_mask[1]) {
raster_config_1 |=
S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
} else {
raster_config_1 |=
S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
--
2.7.4
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