We don't push UBOs on Gen6 currently, so there's no need for the
larger alignment value.
Cc: "17.2" <mesa-sta...@lists.freedesktop.org>
---
src/mesa/drivers/dri/i965/brw_context.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index 60b14571ed0..9c4e91fe3cd 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -616,7 +616,7 @@ brw_initialize_context_constants(struct brw_context *brw)
* In order to push UBO data, 3DSTATE_CONSTANT_XS imposes an additional
* restriction: the start of the buffer needs to be 32B aligned.
*/
- ctx->Const.UniformBufferOffsetAlignment = 32;
+ ctx->Const.UniformBufferOffsetAlignment = brw->gen >= 7 ? 32 : 16;
/* ShaderStorageBufferOffsetAlignment should be a cacheline (64 bytes) so
* that we can safely have the CPU and GPU writing the same SSBO on
--
2.14.0
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