From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeonsi/si_compute.c | 2 +-
src/gallium/drivers/radeonsi/si_descriptors.c | 24 ++++++++++++------------
src/gallium/drivers/radeonsi/si_pipe.h | 2 +-
src/gallium/drivers/radeonsi/si_state.h | 6 +++---
src/gallium/drivers/radeonsi/si_state_draw.c | 8 ++++----
5 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_compute.c
b/src/gallium/drivers/radeonsi/si_compute.c
index fba02fa..5efdd39 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -804,21 +804,21 @@ static void si_launch_grid(
si_initialize_compute(sctx);
if (sctx->b.flags)
si_emit_cache_flush(sctx);
if (!si_switch_compute_shader(sctx, program, &program->shader,
code_object, info->pc))
return;
si_upload_compute_shader_descriptors(sctx);
- si_emit_compute_shader_userdata(sctx);
+ si_emit_compute_shader_pointers(sctx);
if (si_is_atom_dirty(sctx, sctx->atoms.s.render_cond)) {
sctx->atoms.s.render_cond->emit(&sctx->b,
sctx->atoms.s.render_cond);
si_set_atom_dirty(sctx, sctx->atoms.s.render_cond, false);
}
if ((program->input_size ||
program->ir_type == PIPE_SHADER_IR_NATIVE) &&
unlikely(!si_upload_compute_input(sctx, code_object, info))) {
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 917b0e1..64bb9f6 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -1168,21 +1168,21 @@ bool si_upload_vertex_buffer_descriptors(struct
si_context *sctx)
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
(struct
r600_resource*)vb->buffer.resource,
RADEON_USAGE_READ,
RADEON_PRIO_VERTEX_BUFFER);
}
}
/* Don't flush the const cache. It would have a very negative effect
* on performance (confirmed by testing). New descriptors are always
* uploaded to a fresh new buffer, so I don't think flushing the const
* cache is needed. */
- si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
+ si_mark_atom_dirty(sctx, &sctx->shader_pointers.atom);
if (sctx->b.chip_class >= CIK)
sctx->prefetch_L2 = true;
sctx->vertex_buffers_dirty = false;
sctx->vertex_buffer_pointer_dirty = true;
return true;
}
/* CONSTANT BUFFERS */
@@ -2091,37 +2091,37 @@ void si_update_all_texture_descriptors(struct
si_context *sctx)
static void si_mark_shader_pointers_dirty(struct si_context *sctx,
unsigned shader)
{
sctx->shader_pointers_dirty |=
u_bit_consecutive(SI_DESCS_FIRST_SHADER + shader *
SI_NUM_SHADER_DESCS,
SI_NUM_SHADER_DESCS);
if (shader == PIPE_SHADER_VERTEX)
sctx->vertex_buffer_pointer_dirty = sctx->vertex_buffers.buffer
!= NULL;
- si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
+ si_mark_atom_dirty(sctx, &sctx->shader_pointers.atom);
}
-static void si_shader_userdata_begin_new_cs(struct si_context *sctx)
+static void si_shader_pointers_begin_new_cs(struct si_context *sctx)
{
sctx->shader_pointers_dirty = u_bit_consecutive(0, SI_NUM_DESCS);
sctx->vertex_buffer_pointer_dirty = sctx->vertex_buffers.buffer != NULL;
- si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
+ si_mark_atom_dirty(sctx, &sctx->shader_pointers.atom);
}
/* Set a base register address for user data constants in the given shader.
* This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
*/
static void si_set_user_data_base(struct si_context *sctx,
unsigned shader, uint32_t new_base)
{
- uint32_t *base = &sctx->shader_userdata.sh_base[shader];
+ uint32_t *base = &sctx->shader_pointers.sh_base[shader];
if (*base != new_base) {
*base = new_base;
if (new_base) {
si_mark_shader_pointers_dirty(sctx, shader);
if (shader == PIPE_SHADER_VERTEX)
sctx->last_vs_state = ~0;
}
@@ -2178,25 +2178,25 @@ static void si_emit_shader_pointer(struct si_context
*sctx,
va = desc->buffer->gpu_address +
desc->buffer_offset;
radeon_emit(cs, PKT3(PKT3_SET_SH_REG, 2, 0));
radeon_emit(cs, (sh_base + desc->shader_userdata_offset -
SI_SH_REG_OFFSET) >> 2);
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
}
-void si_emit_graphics_shader_userdata(struct si_context *sctx,
+void si_emit_graphics_shader_pointers(struct si_context *sctx,
struct r600_atom *atom)
{
unsigned mask;
- uint32_t *sh_base = sctx->shader_userdata.sh_base;
+ uint32_t *sh_base = sctx->shader_pointers.sh_base;
struct si_descriptors *descs;
descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
if (sctx->shader_pointers_dirty & (1 << SI_DESCS_RW_BUFFERS)) {
si_emit_shader_pointer(sctx, descs,
R_00B030_SPI_SHADER_USER_DATA_PS_0);
si_emit_shader_pointer(sctx, descs,
R_00B130_SPI_SHADER_USER_DATA_VS_0);
@@ -2236,21 +2236,21 @@ void si_emit_graphics_shader_userdata(struct si_context
*sctx,
sctx->shader_pointers_dirty &=
~u_bit_consecutive(SI_DESCS_RW_BUFFERS, SI_DESCS_FIRST_COMPUTE);
if (sctx->vertex_buffer_pointer_dirty) {
si_emit_shader_pointer(sctx, &sctx->vertex_buffers,
sh_base[PIPE_SHADER_VERTEX]);
sctx->vertex_buffer_pointer_dirty = false;
}
}
-void si_emit_compute_shader_userdata(struct si_context *sctx)
+void si_emit_compute_shader_pointers(struct si_context *sctx)
{
unsigned base = R_00B900_COMPUTE_USER_DATA_0;
struct si_descriptors *descs = sctx->descriptors;
unsigned compute_mask =
u_bit_consecutive(SI_DESCS_FIRST_COMPUTE, SI_NUM_SHADER_DESCS);
unsigned mask = sctx->shader_pointers_dirty & compute_mask;
while (mask) {
unsigned i = u_bit_scan(&mask);
@@ -2877,22 +2877,22 @@ void si_init_all_descriptors(struct si_context *sctx)
sctx->b.b.create_texture_handle = si_create_texture_handle;
sctx->b.b.delete_texture_handle = si_delete_texture_handle;
sctx->b.b.make_texture_handle_resident =
si_make_texture_handle_resident;
sctx->b.b.create_image_handle = si_create_image_handle;
sctx->b.b.delete_image_handle = si_delete_image_handle;
sctx->b.b.make_image_handle_resident = si_make_image_handle_resident;
sctx->b.invalidate_buffer = si_invalidate_buffer;
sctx->b.rebind_buffer = si_rebind_buffer;
/* Shader user data. */
- si_init_atom(sctx, &sctx->shader_userdata.atom,
&sctx->atoms.s.shader_userdata,
- si_emit_graphics_shader_userdata);
+ si_init_atom(sctx, &sctx->shader_pointers.atom,
&sctx->atoms.s.shader_pointers,
+ si_emit_graphics_shader_pointers);
/* Set default and immutable mappings. */
si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
R_00B130_SPI_SHADER_USER_DATA_VS_0);
if (sctx->b.chip_class >= GFX9) {
si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL,
R_00B430_SPI_SHADER_USER_DATA_LS_0);
si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY,
R_00B330_SPI_SHADER_USER_DATA_ES_0);
} else {
@@ -2909,21 +2909,21 @@ bool si_upload_graphics_shader_descriptors(struct
si_context *sctx)
const unsigned mask = u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE);
unsigned dirty = sctx->descriptors_dirty & mask;
/* Assume nothing will go wrong: */
sctx->shader_pointers_dirty |= dirty;
while (dirty) {
unsigned i = u_bit_scan(&dirty);
if (!si_upload_descriptors(sctx, &sctx->descriptors[i],
- &sctx->shader_userdata.atom))
+ &sctx->shader_pointers.atom))
return false;
}
sctx->descriptors_dirty &= ~mask;
si_upload_bindless_descriptors(sctx);
return true;
}
@@ -2983,21 +2983,21 @@ void si_all_descriptors_begin_new_cs(struct si_context
*sctx)
si_buffer_resources_begin_new_cs(sctx,
&sctx->const_and_shader_buffers[i]);
si_sampler_views_begin_new_cs(sctx, &sctx->samplers[i].views);
si_image_views_begin_new_cs(sctx, &sctx->images[i]);
}
si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers);
si_vertex_buffers_begin_new_cs(sctx);
for (i = 0; i < SI_NUM_DESCS; ++i)
si_descriptors_begin_new_cs(sctx, &sctx->descriptors[i]);
- si_shader_userdata_begin_new_cs(sctx);
+ si_shader_pointers_begin_new_cs(sctx);
}
void si_set_active_descriptors(struct si_context *sctx, unsigned desc_idx,
uint64_t new_active_mask)
{
struct si_descriptors *desc = &sctx->descriptors[desc_idx];
/* Ignore no-op updates and updates that disable all slots. */
if (!new_active_mask ||
new_active_mask == u_bit_consecutive64(desc->first_active_slot,
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index d213886..20ea194 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -297,21 +297,21 @@ struct si_context {
struct si_framebuffer framebuffer;
struct si_sample_locs msaa_sample_locs;
struct r600_atom db_render_state;
struct r600_atom msaa_config;
struct si_sample_mask sample_mask;
struct r600_atom cb_render_state;
unsigned last_cb_target_mask;
struct si_blend_color blend_color;
struct r600_atom clip_regs;
struct si_clip_state clip_state;
- struct si_shader_data shader_userdata;
+ struct si_shader_data shader_pointers;
struct si_stencil_ref stencil_ref;
struct r600_atom spi_map;
/* Precomputed states. */
struct si_pm4_state *init_config;
struct si_pm4_state *init_config_gs_rings;
bool init_config_has_vgt_flush;
struct si_pm4_state *vgt_shader_config[4];
/* shaders */
diff --git a/src/gallium/drivers/radeonsi/si_state.h
b/src/gallium/drivers/radeonsi/si_state.h
index 9fbede7..c6c9d98 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -146,21 +146,21 @@ union si_state_atoms {
struct r600_atom *streamout_enable; /* must be after
streamout_begin */
struct r600_atom *framebuffer;
struct r600_atom *msaa_sample_locs;
struct r600_atom *db_render_state;
struct r600_atom *msaa_config;
struct r600_atom *sample_mask;
struct r600_atom *cb_render_state;
struct r600_atom *blend_color;
struct r600_atom *clip_regs;
struct r600_atom *clip_state;
- struct r600_atom *shader_userdata;
+ struct r600_atom *shader_pointers;
struct r600_atom *scissors;
struct r600_atom *viewports;
struct r600_atom *stencil_ref;
struct r600_atom *spi_map;
struct r600_atom *scratch_state;
} s;
struct r600_atom *array[0];
};
#define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct r600_atom*))
@@ -329,23 +329,23 @@ bool si_upload_vertex_buffer_descriptors(struct
si_context *sctx);
bool si_upload_graphics_shader_descriptors(struct si_context *sctx);
bool si_upload_compute_shader_descriptors(struct si_context *sctx);
void si_release_all_descriptors(struct si_context *sctx);
void si_all_descriptors_begin_new_cs(struct si_context *sctx);
void si_all_resident_buffers_begin_new_cs(struct si_context *sctx);
void si_upload_const_buffer(struct si_context *sctx, struct r600_resource
**rbuffer,
const uint8_t *ptr, unsigned size, uint32_t
*const_offset);
void si_update_all_texture_descriptors(struct si_context *sctx);
void si_shader_change_notify(struct si_context *sctx);
void si_update_needs_color_decompress_masks(struct si_context *sctx);
-void si_emit_graphics_shader_userdata(struct si_context *sctx,
+void si_emit_graphics_shader_pointers(struct si_context *sctx,
struct r600_atom *atom);
-void si_emit_compute_shader_userdata(struct si_context *sctx);
+void si_emit_compute_shader_pointers(struct si_context *sctx);
void si_set_rw_buffer(struct si_context *sctx,
uint slot, const struct pipe_constant_buffer *input);
void si_set_active_descriptors(struct si_context *sctx, unsigned desc_idx,
uint64_t new_active_mask);
void si_set_active_descriptors_for_shader(struct si_context *sctx,
struct si_shader_selector *sel);
bool si_bindless_descriptor_can_reclaim_slab(void *priv,
struct pb_slab_entry *entry);
struct pb_slab *si_bindless_descriptor_slab_alloc(void *priv, unsigned heap,
unsigned entry_size,
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 06a18c1..ae054d8 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -98,21 +98,21 @@ static void si_emit_derived_tess_state(struct si_context
*sctx,
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
struct si_shader *ls_current;
struct si_shader_selector *ls;
/* The TES pointer will only be used for sctx->last_tcs.
* It would be wrong to think that TCS = TES. */
struct si_shader_selector *tcs =
sctx->tcs_shader.cso ? sctx->tcs_shader.cso :
sctx->tes_shader.cso;
unsigned tess_uses_primid =
sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id;
bool has_primid_instancing_bug = sctx->b.chip_class == SI &&
sctx->b.screen->info.max_se == 1;
- unsigned tes_sh_base =
sctx->shader_userdata.sh_base[PIPE_SHADER_TESS_EVAL];
+ unsigned tes_sh_base =
sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
unsigned num_tcs_input_cp = info->vertices_per_patch;
unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
unsigned num_tcs_patch_outputs;
unsigned input_vertex_size, output_vertex_size,
pervertex_output_patch_size;
unsigned input_patch_size, output_patch_size, output_patch0_offset;
unsigned perpatch_output_offset, lds_size;
unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
unsigned offchip_layout, hardware_lds_size, ls_hs_config;
/* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
@@ -560,21 +560,21 @@ static void si_emit_rasterizer_prim_state(struct
si_context *sctx)
static void si_emit_vs_state(struct si_context *sctx,
const struct pipe_draw_info *info)
{
sctx->current_vs_state &= C_VS_STATE_INDEXED;
sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->index_size);
if (sctx->current_vs_state != sctx->last_vs_state) {
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
radeon_set_sh_reg(cs,
- sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX] +
+ sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] +
SI_SGPR_VS_STATE_BITS * 4,
sctx->current_vs_state);
sctx->last_vs_state = sctx->current_vs_state;
}
}
static void si_emit_draw_registers(struct si_context *sctx,
const struct pipe_draw_info *info,
unsigned num_patches)
@@ -633,21 +633,21 @@ static void si_emit_draw_registers(struct si_context
*sctx,
}
static void si_emit_draw_packets(struct si_context *sctx,
const struct pipe_draw_info *info,
struct pipe_resource *indexbuf,
unsigned index_size,
unsigned index_offset)
{
struct pipe_draw_indirect_info *indirect = info->indirect;
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
- unsigned sh_base_reg =
sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
+ unsigned sh_base_reg =
sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
bool render_cond_bit = sctx->b.render_cond &&
!sctx->b.render_cond_force_off;
uint32_t index_max_size = 0;
uint64_t index_va = 0;
if (info->count_from_stream_output) {
struct r600_so_target *t =
(struct r600_so_target*)info->count_from_stream_output;
uint64_t va = t->buf_filled_size->gpu_address +
t->buf_filled_size_offset;
@@ -1401,21 +1401,21 @@ void si_draw_vbo(struct pipe_context *ctx, const struct
pipe_draw_info *info)
* SET packets are processed in parallel with previous draw
calls.
* Sequence:
* - process SET packets except SET_SH packets for shader
pointers
* - flush caches and wait for previous draw calls
* - start CE dumps (might already be ongoing if there is no
CE-DE barrier)
* - start prefetches
* - process SET_SH packets for shader pointers
* - wait for CE dumps
* - draw
*/
- struct r600_atom *shader_pointers = &sctx->shader_userdata.atom;
+ struct r600_atom *shader_pointers = &sctx->shader_pointers.atom;
/* Emit all states except shader pointers. */
si_emit_all_states(sctx, info, 1 << shader_pointers->id);
if (!si_cache_flush_and_prefetch(sctx))
return;
/* Set shader pointers last. */
if (si_is_atom_dirty(sctx, shader_pointers)) {
shader_pointers->emit(&sctx->b, NULL);
--
2.7.4
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