Reviewed-by: Jordan Justen <jordan.l.jus...@intel.com>
On 2017-08-02 13:35:35, Jason Ekstrand wrote:
> The only force tiling flag we really care about is LAYOUT_TILING_NONE.
> The others don't actually do anything but add confusion.
> ---
> src/mesa/drivers/dri/i965/intel_fbo.c | 3 +--
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 19 ++++---------------
> src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 ---
> src/mesa/drivers/dri/i965/intel_tex.c | 2 +-
> src/mesa/drivers/dri/i965/intel_tex_image.c | 2 +-
> src/mesa/drivers/dri/i965/intel_tex_validate.c | 3 +--
> 6 files changed, 8 insertions(+), 24 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c
> b/src/mesa/drivers/dri/i965/intel_fbo.c
> index 9e27593..71bc90d 100644
> --- a/src/mesa/drivers/dri/i965/intel_fbo.c
> +++ b/src/mesa/drivers/dri/i965/intel_fbo.c
> @@ -944,8 +944,7 @@ intel_renderbuffer_move_to_temp(struct brw_context *brw,
> struct intel_mipmap_tree *new_mt;
> int width, height, depth;
>
> - uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD |
> - MIPTREE_LAYOUT_TILING_ANY;
> + uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
>
> intel_get_image_dims(rb->TexImage, &width, &height, &depth);
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 305912c..7e87099 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -628,16 +628,6 @@ make_separate_stencil_surface(struct brw_context *brw,
> return true;
> }
>
> -static bool
> -force_linear_tiling(uint32_t layout_flags)
> -{
> - /* ANY includes NONE and Y bit. */
> - if (layout_flags & MIPTREE_LAYOUT_TILING_Y)
> - return false;
> -
> - return layout_flags & MIPTREE_LAYOUT_TILING_NONE;
> -}
> -
> static struct intel_mipmap_tree *
> miptree_create(struct brw_context *brw,
> GLenum target,
> @@ -663,7 +653,7 @@ miptree_create(struct brw_context *brw,
> const GLenum base_format = _mesa_get_format_base_format(format);
> if ((base_format == GL_DEPTH_COMPONENT ||
> base_format == GL_DEPTH_STENCIL) &&
> - !force_linear_tiling(layout_flags)) {
> + !(layout_flags & MIPTREE_LAYOUT_TILING_NONE)) {
> /* Fix up the Z miptree format for how we're splitting out separate
> * stencil. Gen7 expects there to be no stencil bits in its depth
> buffer.
> */
> @@ -699,7 +689,8 @@ miptree_create(struct brw_context *brw,
> if (layout_flags & MIPTREE_LAYOUT_ACCELERATED_UPLOAD)
> alloc_flags |= BO_ALLOC_FOR_RENDER;
>
> - isl_tiling_flags_t tiling_flags = force_linear_tiling(layout_flags) ?
> + isl_tiling_flags_t tiling_flags =
> + (layout_flags & MIPTREE_LAYOUT_TILING_NONE) ?
> ISL_TILING_LINEAR_BIT : ISL_TILING_ANY_MASK;
>
> /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
> @@ -823,7 +814,6 @@ intel_miptree_create_for_bo(struct brw_context *brw,
> /* The BO already has a tiling format and we shouldn't confuse the lower
> * layers by making it try to find a tiling format again.
> */
> - assert((layout_flags & MIPTREE_LAYOUT_TILING_ANY) == 0);
> assert((layout_flags & MIPTREE_LAYOUT_TILING_NONE) == 0);
>
> mt = make_surface(brw, target, format,
> @@ -1059,8 +1049,7 @@ intel_miptree_create_for_renderbuffer(struct
> brw_context *brw,
> struct intel_mipmap_tree *mt;
> uint32_t depth = 1;
> GLenum target = num_samples > 1 ? GL_TEXTURE_2D_MULTISAMPLE :
> GL_TEXTURE_2D;
> - const uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD |
> - MIPTREE_LAYOUT_TILING_ANY;
> + const uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
>
> mt = intel_miptree_create(brw, target, format, 0, 0,
> width, height, depth, num_samples,
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> index 70acb96..28e8e01 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> @@ -352,10 +352,7 @@ enum {
> MIPTREE_LAYOUT_ACCELERATED_UPLOAD = 1 << 0,
> MIPTREE_LAYOUT_DISABLE_AUX = 1 << 3,
>
> - MIPTREE_LAYOUT_TILING_Y = 1 << 5,
> MIPTREE_LAYOUT_TILING_NONE = 1 << 6,
> - MIPTREE_LAYOUT_TILING_ANY = MIPTREE_LAYOUT_TILING_Y |
> - MIPTREE_LAYOUT_TILING_NONE,
> };
>
> struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
> diff --git a/src/mesa/drivers/dri/i965/intel_tex.c
> b/src/mesa/drivers/dri/i965/intel_tex.c
> index 7ce2ceb..686b31c 100644
> --- a/src/mesa/drivers/dri/i965/intel_tex.c
> +++ b/src/mesa/drivers/dri/i965/intel_tex.c
> @@ -150,7 +150,7 @@ intel_alloc_texture_storage(struct gl_context *ctx,
> 0, levels - 1,
> width, height, depth,
> MAX2(num_samples, 1),
> - MIPTREE_LAYOUT_TILING_ANY);
> + 0);
>
> if (intel_texobj->mt == NULL) {
> return false;
> diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c
> b/src/mesa/drivers/dri/i965/intel_tex_image.c
> index beed160..598d39c 100644
> --- a/src/mesa/drivers/dri/i965/intel_tex_image.c
> +++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
> @@ -124,7 +124,7 @@ intel_miptree_create_for_teximage(struct brw_context *brw,
> height,
> depth,
> MAX2(intelImage->base.Base.NumSamples, 1),
> - layout_flags | MIPTREE_LAYOUT_TILING_ANY);
> + layout_flags);
> }
>
> static void
> diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c
> b/src/mesa/drivers/dri/i965/intel_tex_validate.c
> index a156f73..1e735c9 100644
> --- a/src/mesa/drivers/dri/i965/intel_tex_validate.c
> +++ b/src/mesa/drivers/dri/i965/intel_tex_validate.c
> @@ -136,8 +136,7 @@ intel_finalize_mipmap_tree(struct brw_context *brw,
> GLuint unit)
> _mesa_get_format_name(firstImage->base.Base.TexFormat),
> width, height, depth, validate_last_level + 1);
>
> - const uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD |
> - MIPTREE_LAYOUT_TILING_ANY;
> + const uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
> intelObj->mt = intel_miptree_create(brw,
> intelObj->base.Target,
> firstImage->base.Base.TexFormat,
> --
> 2.5.0.400.gff86faf
>
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> mesa-dev@lists.freedesktop.org
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