Thanks to Chris Wilson for pointing this out.
Cc: Jason Ekstrand <ja...@jlekstrand.net>
---
src/intel/common/gen_clflush.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/src/intel/common/gen_clflush.h b/src/intel/common/gen_clflush.h
index 9b971cac37e..84cc2f2f132 100644
--- a/src/intel/common/gen_clflush.h
+++ b/src/intel/common/gen_clflush.h
@@ -50,6 +50,17 @@ static inline void
gen_invalidate_range(void *start, size_t size)
{
gen_clflush_range(start, size);
+
+ /* Modern Atom CPUs (Baytrail+) have issues with clflush serialization,
+ * where mfence is not a sufficient synchronization barrier. We must
+ * double clflush the last cacheline. This guarantees it will be ordered
+ * after the preceding clflushes, and then the mfence guards against
+ * prefetches crossing the clflush boundary.
+ *
+ * See kernel commit 396f5d62d1a5fd99421855a08ffdef8edb43c76e and
+ * https://bugs.freedesktop.org/show_bug.cgi?id=92845.
+ */
+ __builtin_ia32_clflush(start + size - 1);
__builtin_ia32_mfence();
}
--
2.13.2
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