Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/gen7_misc_state.c | 20 ++++++---------
src/mesa/drivers/dri/i965/gen8_depth_state.c | 26 ++++++-------------
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 36 ++++++++++++++++-----------
3 files changed, 37 insertions(+), 45 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c
b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index d417f7c299..f272e05860 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -83,7 +83,8 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
break;
case GL_TEXTURE_3D:
assert(mt);
- depth = MAX2(mt->logical_depth0, 1);
+ depth = mt->surf.size > 0 ? mt->surf.logical_level0_px.depth :
+ MAX2(mt->logical_depth0, 1);
/* fallthrough */
default:
surftype = translate_tex_target(gl_target);
@@ -94,7 +95,10 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
lod = irb ? irb->mt_level - irb->mt->first_level : 0;
- if (mt) {
+ if (mt && mt->surf.size > 0) {
+ width = mt->surf.logical_level0_px.width;
+ height = mt->surf.logical_level0_px.height;
+ } else if (mt) {
width = mt->logical_width0;
height = mt->logical_height0;
}
@@ -170,19 +174,9 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
BEGIN_BATCH(3);
OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
- /* The stencil buffer has quirky pitch requirements. From the
- * Sandybridge PRM, Volume 2 Part 1, page 329 (3DSTATE_STENCIL_BUFFER
- * dword 1 bits 16:0 - Surface Pitch):
- *
- * The pitch must be set to 2x the value computed based on width, as
- * the stencil buffer is stored with two rows interleaved.
- *
- * While the Ivybridge PRM lacks this comment, the BSpec contains the
- * same text, and experiments indicate that this is necessary.
- */
OUT_BATCH(enabled |
mocs << 25 |
- (2 * stencil_mt->pitch - 1));
+ (stencil_mt->surf.row_pitch - 1));
OUT_RELOC(stencil_mt->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c
b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index f697ec332a..7729fac091 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -114,25 +114,11 @@ emit_depth_packets(struct brw_context *brw,
BEGIN_BATCH(5);
OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (5 - 2));
- /* The stencil buffer has quirky pitch requirements. From the Graphics
- * BSpec: vol2a.11 3D Pipeline Windower > Early Depth/Stencil Processing
- * > Depth/Stencil Buffer State > 3DSTATE_STENCIL_BUFFER [DevIVB+],
- * field "Surface Pitch":
- *
- * The pitch must be set to 2x the value computed based on width, as
- * the stencil buffer is stored with two rows interleaved.
- *
- * (Note that it is not 100% clear whether this intended to apply to
- * Gen7; the BSpec flags this comment as "DevILK,DevSNB" (which would
- * imply that it doesn't), however the comment appears on a "DevIVB+"
- * page (which would imply that it does). Experiments with the hardware
- * indicate that it does.
- */
OUT_BATCH(HSW_STENCIL_ENABLED | mocs_wb << 22 |
- (2 * stencil_mt->pitch - 1));
+ (stencil_mt->surf.row_pitch - 1));
OUT_RELOC64(stencil_mt->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
- OUT_BATCH(stencil_mt ? stencil_mt->qpitch >> 2 : 0);
+ OUT_BATCH(stencil_mt->surf.array_pitch_el_rows >> 2);
ADVANCE_BATCH();
}
@@ -192,7 +178,8 @@ gen8_emit_depth_stencil_hiz(struct brw_context *brw,
break;
case GL_TEXTURE_3D:
assert(mt);
- depth = MAX2(mt->logical_depth0, 1);
+ depth = mt->surf.size > 0 ? mt->surf.logical_level0_px.depth :
+ MAX2(mt->logical_depth0, 1);
surftype = translate_tex_target(gl_target);
break;
case GL_TEXTURE_1D_ARRAY:
@@ -215,7 +202,10 @@ gen8_emit_depth_stencil_hiz(struct brw_context *brw,
lod = irb ? irb->mt_level - irb->mt->first_level : 0;
- if (mt) {
+ if (mt && mt->surf.size > 0) {
+ width = mt->surf.logical_level0_px.width;
+ height = mt->surf.logical_level0_px.height;
+ } else if (mt) {
width = mt->logical_width0;
height = mt->logical_height0;
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index a1545a5857..a401af0423 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -730,7 +730,7 @@ miptree_create(struct brw_context *brw,
GLuint num_samples,
uint32_t layout_flags)
{
- if (brw->gen == 6 && format == MESA_FORMAT_S_UINT8)
+ if (format == MESA_FORMAT_S_UINT8)
return make_surface(brw, target, format, first_level, last_level,
width0, height0, depth0, num_samples, ISL_TILING_W,
ISL_SURF_USAGE_STENCIL_BIT |
@@ -2749,36 +2749,44 @@ intel_update_r8stencil(struct brw_context *brw,
!src->r8stencil_needs_update)
return;
+ assert(src->surf.size > 0);
+
if (!mt->r8stencil_mt) {
const uint32_t r8stencil_flags =
MIPTREE_LAYOUT_ACCELERATED_UPLOAD | MIPTREE_LAYOUT_TILING_Y |
MIPTREE_LAYOUT_DISABLE_AUX;
assert(brw->gen > 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
- mt->r8stencil_mt = intel_miptree_create(brw,
- src->target,
- MESA_FORMAT_R_UINT8,
- src->first_level,
- src->last_level,
- src->logical_width0,
- src->logical_height0,
- src->logical_depth0,
- src->num_samples,
- r8stencil_flags);
+ mt->r8stencil_mt = intel_miptree_create(
+ brw,
+ src->target,
+ MESA_FORMAT_R_UINT8,
+ src->first_level, src->last_level,
+ src->surf.logical_level0_px.width,
+ src->surf.logical_level0_px.height,
+ src->surf.dim == ISL_SURF_DIM_3D ?
+ src->surf.logical_level0_px.depth :
+ src->surf.logical_level0_px.array_len,
+ src->surf.samples,
+ r8stencil_flags);
assert(mt->r8stencil_mt);
}
struct intel_mipmap_tree *dst = mt->r8stencil_mt;
for (int level = src->first_level; level <= src->last_level; level++) {
- const unsigned depth = src->level[level].depth;
+ const unsigned depth = src->surf.dim == ISL_SURF_DIM_3D ?
+ minify(src->surf.phys_level0_sa.depth, level) :
+ src->surf.phys_level0_sa.array_len;
for (unsigned layer = 0; layer < depth; layer++) {
brw_blorp_copy_miptrees(brw,
src, level, layer,
dst, level, layer,
0, 0, 0, 0,
- minify(src->logical_width0, level),
- minify(src->logical_height0, level));
+ minify(src->surf.logical_level0_px.width,
+ level),
+ minify(src->surf.logical_level0_px.height,
+ level));
}
}
--
2.11.0
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