On 12.06.2017 19:37, Brian Paul wrote:
I've since discovered the fragment shader sample mask input (which
corresponds to gl_SampleMaskIn).
---
src/gallium/docs/source/tgsi.rst | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst
index 310b49d..7ca07dd 100644
--- a/src/gallium/docs/source/tgsi.rst
+++ b/src/gallium/docs/source/tgsi.rst
@@ -3328,10 +3328,17 @@ the center of the fragment.
TGSI_SEMANTIC_SAMPLEMASK
""""""""""""""""""""""""
-For fragment shaders, this semantic label indicates that an output contains
-the sample mask used to disable further sample processing. The output's
-type is uint[4] but only the X component is used (i.e. gl_SampleMask[0]).
-Each bit corresponds to one sample position (up to 32x MSAA is supported).
+For fragment shaders, this semantic label can be applied to either a
+shader input or output.
+
+For an input, the sample mask indicates the set of samples covered by
+the current primitive. If MSAA is not enabled, the value is (~0, ~0, ~0, ~0).
This doesn't match radeonsi behavior. I think you may get (1, ?, ?, ?)
without MSAA, although I've never tried, and if DX says you get ~0, then
perhaps that's actually what our hardware does.
But what I'm certain about is that trying to use the yzw components will
lead to a shader compiler assertion :-)
Cheers,
Nicolai
+
+For an output, the sample mask is used to disable further sample processing.
+
+For both inputs and outputs, the register type is uint[4] but only the X
+component is used (i.e. gl_SampleMask[0]). Each bit corresponds to one
+sample position (up to 32x MSAA is supported).
TGSI_SEMANTIC_INVOCATIONID
""""""""""""""""""""""""""
--
Lerne, wie die Welt wirklich ist,
Aber vergiss niemals, wie sie sein sollte.
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