From: Dave Airlie <airl...@redhat.com>
These are just some register changes ported from radeonsi for gfx9.
---
src/amd/vulkan/radv_cmd_buffer.c | 20 +++++++++++++++-----
src/amd/vulkan/radv_device.c | 4 ++++
src/amd/vulkan/radv_pipeline.c | 3 ++-
3 files changed, 21 insertions(+), 6 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 8b61992..22e67f9 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1494,8 +1494,13 @@ static void radv_emit_primitive_reset_state(struct
radv_cmd_buffer *cmd_buffer,
if (primitive_reset_en != cmd_buffer->state.last_primitive_reset_en) {
cmd_buffer->state.last_primitive_reset_en = primitive_reset_en;
- radeon_set_context_reg(cmd_buffer->cs,
R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
- primitive_reset_en);
+ if (cmd_buffer->device->physical_device->rad_info.chip_class >=
GFX9) {
+ radeon_set_uconfig_reg(cmd_buffer->cs,
R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
+ primitive_reset_en);
+ } else {
+ radeon_set_context_reg(cmd_buffer->cs,
R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
+ primitive_reset_en);
+ }
}
if (primitive_reset_en) {
@@ -1902,7 +1907,7 @@ static void emit_gfx_buffer_state(struct radv_cmd_buffer
*cmd_buffer)
device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2,
0));
radeon_emit(cmd_buffer->cs, va);
- radeon_emit(cmd_buffer->cs, (va >> 32) & 0xffff);
+ radeon_emit(cmd_buffer->cs, va >> 32);
radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
} else
si_init_config(cmd_buffer);
@@ -2655,8 +2660,13 @@ void radv_CmdDrawIndexed(
MAYBE_UNUSED unsigned cdw_max =
radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
- radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
- radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
+ if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
+ radeon_set_uconfig_reg_idx(cmd_buffer->cs,
R_03090C_VGT_INDEX_TYPE,
+ 2, cmd_buffer->state.index_type);
+ } else {
+ radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
+ radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
+ }
struct ac_userdata_info *loc =
radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
AC_UD_VS_BASE_VERTEX_START_INSTANCE);
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index f919a24..5528bc5 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1728,6 +1728,10 @@ radv_get_preamble_cs(struct radv_queue *queue,
S_030938_SIZE(tess_factor_ring_size / 4));
radeon_set_uconfig_reg(cs,
R_030940_VGT_TF_MEMORY_BASE,
tf_va >> 8);
+ if
(queue->device->physical_device->rad_info.chip_class >= GFX9) {
+ radeon_set_uconfig_reg(cs,
R_030944_VGT_TF_MEMORY_BASE_HI,
+ tf_va >> 40);
+ }
radeon_set_uconfig_reg(cs,
R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
} else {
radeon_set_config_reg(cs,
R_008988_VGT_TF_RING_SIZE,
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 1f5fe50..6671acd6 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1332,11 +1332,12 @@ radv_pipeline_init_multisample_state(struct
radv_pipeline *pipeline,
S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
+ ms->pa_sc_mode_cntl_0 =
S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class
>= GFX9);
if (ms->num_samples > 1) {
unsigned log_samples = util_logbase2(ms->num_samples);
unsigned log_ps_iter_samples =
util_logbase2(util_next_power_of_two(ps_iter_samples));
- ms->pa_sc_mode_cntl_0 = S_028A48_MSAA_ENABLE(1);
+ ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /*
CM_R_028BDC_PA_SC_LINE_CNTL */
ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
--
2.9.4
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