From: Marek Olšák <marek.ol...@amd.com> --- src/gallium/drivers/radeonsi/si_pipe.h | 30 ++++++++++++++----------- src/gallium/drivers/radeonsi/si_state_shaders.c | 6 ++--- 2 files changed, 19 insertions(+), 17 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 9364ef2..c5e6e7d 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -484,40 +484,44 @@ si_is_atom_dirty(struct si_context *sctx, return sctx->dirty_atoms & bit; } static inline void si_mark_atom_dirty(struct si_context *sctx, struct r600_atom *atom) { si_set_atom_dirty(sctx, atom, true); } -static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx) +static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx) { if (sctx->gs_shader.cso) - return &sctx->gs_shader.cso->info; - else if (sctx->tes_shader.cso) - return &sctx->tes_shader.cso->info; - else if (sctx->vs_shader.cso) - return &sctx->vs_shader.cso->info; - else - return NULL; + return &sctx->gs_shader; + if (sctx->tes_shader.cso) + return &sctx->tes_shader; + + return &sctx->vs_shader; +} + +static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx) +{ + struct si_shader_ctx_state *vs = si_get_vs(sctx); + + return vs->cso ? &vs->cso->info : NULL; } static inline struct si_shader* si_get_vs_state(struct si_context *sctx) { - if (sctx->gs_shader.current) + if (sctx->gs_shader.cso) return sctx->gs_shader.cso->gs_copy_shader; - else if (sctx->tes_shader.current) - return sctx->tes_shader.current; - else - return sctx->vs_shader.current; + + struct si_shader_ctx_state *vs = si_get_vs(sctx); + return vs->current ? vs->current : NULL; } static inline unsigned si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size) { unsigned alignment, tcc_cache_line_size; /* If the upload size is less than the cache line size (e.g. 16, 32), * the whole thing will fit into a cache line if we align it to its size. * The idea is that multiple small uploads can share a cache line. diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index 7ed6722..078b5e6 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -2147,24 +2147,22 @@ static void *si_create_shader_selector(struct pipe_context *ctx, else util_queue_add_job(&sscreen->shader_compiler_queue, sel, &sel->ready, si_init_shader_selector_async, NULL); return sel; } static void si_update_streamout_state(struct si_context *sctx) { - struct si_shader_selector *shader_with_so = - sctx->gs_shader.cso ? sctx->gs_shader.cso : - sctx->tes_shader.cso ? sctx->tes_shader.cso : - sctx->vs_shader.cso; + struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso; + if (!shader_with_so) return; sctx->b.streamout.enabled_stream_buffers_mask = shader_with_so->enabled_streamout_buffer_mask; sctx->b.streamout.stride_in_dw = shader_with_so->so.stride; } static void si_bind_vs_shader(struct pipe_context *ctx, void *state) { -- 2.7.4 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev