On Thu, Jun 1, 2017 at 6:52 AM, Dave Airlie <airl...@gmail.com> wrote:
> On 1 June 2017 at 14:43, Dave Airlie <airl...@gmail.com> wrote:
>> From: Dave Airlie <airl...@redhat.com>
>>
>> In prep for GFX9 refactor some of the eop event writing code
>> out.
>
> This triggers an assert, I have to bump some of the command stream size
> checks.
>
> This does change behaviour by emitting 2 EOPs where we used to emit
> one on CIK/VI,
> but it's also what radeonsi seems to do now.
>
> Dave.
Yeah, the change in radv_CmdEndQuery needs the reservation in the
VK_QUERY_TYPE_PIPELINE_STATISTICS case to be bumped from 10 to 16.
With that:
Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
>
>>
>> Signed-off-by: Dave Airlie <airl...@redhat.com>
>> ---
>> src/amd/vulkan/radv_cmd_buffer.c | 22 ++++-------------
>> src/amd/vulkan/radv_private.h | 9 +++++++
>> src/amd/vulkan/radv_query.c | 53
>> ++++++++++++----------------------------
>> src/amd/vulkan/si_cmd_buffer.c | 45 ++++++++++++++++++++++++++++++++++
>> 4 files changed, 74 insertions(+), 55 deletions(-)
>>
>> diff --git a/src/amd/vulkan/radv_cmd_buffer.c
>> b/src/amd/vulkan/radv_cmd_buffer.c
>> index c4d3d7b..43e1a93 100644
>> --- a/src/amd/vulkan/radv_cmd_buffer.c
>> +++ b/src/amd/vulkan/radv_cmd_buffer.c
>> @@ -3233,23 +3233,11 @@ static void write_event(struct radv_cmd_buffer
>> *cmd_buffer,
>> /* TODO: this is overkill. Probably should figure something out from
>> * the stage mask. */
>>
>> - if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK)
>> {
>> - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
>> - radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
>> - EVENT_INDEX(5));
>> - radeon_emit(cs, va);
>> - radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
>> - radeon_emit(cs, 2);
>> - radeon_emit(cs, 0);
>> - }
>> -
>> - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
>> - radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
>> - EVENT_INDEX(5));
>> - radeon_emit(cs, va);
>> - radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
>> - radeon_emit(cs, value);
>> - radeon_emit(cs, 0);
>> + si_cs_emit_write_event_eop(cs,
>> +
>> cmd_buffer->device->physical_device->rad_info.chip_class == CIK,
>> + false,
>> + EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
>> + 1, va, 2, value);
>>
>> assert(cmd_buffer->cs->cdw <= cdw_max);
>> }
>> diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
>> index 264b6c9..6798ee4 100644
>> --- a/src/amd/vulkan/radv_private.h
>> +++ b/src/amd/vulkan/radv_private.h
>> @@ -838,6 +838,15 @@ void si_write_scissors(struct radeon_winsys_cs *cs, int
>> first,
>> uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
>> bool instanced_draw, bool indirect_draw,
>> uint32_t draw_vertex_count);
>> +void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
>> + enum chip_class chip_class,
>> + bool is_mec,
>> + unsigned event, unsigned event_flags,
>> + unsigned data_sel,
>> + uint64_t va,
>> + uint32_t old_fence,
>> + uint32_t new_fence);
>> +
>> void si_emit_wait_fence(struct radeon_winsys_cs *cs,
>> uint64_t va, uint32_t ref,
>> uint32_t mask);
>> diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
>> index 910eedd..708879d 100644
>> --- a/src/amd/vulkan/radv_query.c
>> +++ b/src/amd/vulkan/radv_query.c
>> @@ -1153,13 +1153,11 @@ void radv_CmdEndQuery(
>> radeon_emit(cs, va);
>> radeon_emit(cs, va >> 32);
>>
>> - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
>> - radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
>> - EVENT_INDEX(5));
>> - radeon_emit(cs, avail_va);
>> - radeon_emit(cs, (avail_va >> 32) | EOP_DATA_SEL(1));
>> - radeon_emit(cs, 1);
>> - radeon_emit(cs, 0);
>> + si_cs_emit_write_event_eop(cs,
>> +
>> cmd_buffer->device->physical_device->rad_info.chip_class,
>> + false,
>> + EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
>> + 1, avail_va, 0, 1);
>> break;
>> default:
>> unreachable("ending unhandled query type");
>> @@ -1204,37 +1202,16 @@ void radv_CmdWriteTimestamp(
>> radeon_emit(cs, 1);
>> break;
>> default:
>> - if (mec) {
>> - radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 5, 0));
>> - radeon_emit(cs,
>> EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5));
>> - radeon_emit(cs, 3 << 29);
>> - radeon_emit(cs, query_va);
>> - radeon_emit(cs, query_va >> 32);
>> - radeon_emit(cs, 0);
>> - radeon_emit(cs, 0);
>> -
>> - radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 5, 0));
>> - radeon_emit(cs,
>> EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5));
>> - radeon_emit(cs, 1 << 29);
>> - radeon_emit(cs, avail_va);
>> - radeon_emit(cs, avail_va >> 32);
>> - radeon_emit(cs, 1);
>> - radeon_emit(cs, 0);
>> - } else {
>> - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
>> - radeon_emit(cs,
>> EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5));
>> - radeon_emit(cs, query_va);
>> - radeon_emit(cs, (3 << 29) | ((query_va >> 32) &
>> 0xFFFF));
>> - radeon_emit(cs, 0);
>> - radeon_emit(cs, 0);
>> -
>> - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
>> - radeon_emit(cs,
>> EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5));
>> - radeon_emit(cs, avail_va);
>> - radeon_emit(cs, (1 << 29) | ((avail_va >> 32) &
>> 0xFFFF));
>> - radeon_emit(cs, 1);
>> - radeon_emit(cs, 0);
>> - }
>> + si_cs_emit_write_event_eop(cs,
>> +
>> cmd_buffer->device->physical_device->rad_info.chip_class,
>> + mec,
>> + V_028A90_BOTTOM_OF_PIPE_TS, 0,
>> + 3, query_va, 0, 0);
>> + si_cs_emit_write_event_eop(cs,
>> +
>> cmd_buffer->device->physical_device->rad_info.chip_class,
>> + mec,
>> + V_028A90_BOTTOM_OF_PIPE_TS, 0,
>> + 1, avail_va, 0, 1);
>> break;
>> }
>>
>> diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
>> index 3bf1d39..69f57fd 100644
>> --- a/src/amd/vulkan/si_cmd_buffer.c
>> +++ b/src/amd/vulkan/si_cmd_buffer.c
>> @@ -762,6 +762,51 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer
>> *cmd_buffer,
>>
>> }
>>
>> +void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
>> + enum chip_class chip_class,
>> + bool is_mec,
>> + unsigned event, unsigned event_flags,
>> + unsigned data_sel,
>> + uint64_t va,
>> + uint32_t old_fence,
>> + uint32_t new_fence)
>> +{
>> + unsigned op = EVENT_TYPE(event) |
>> + EVENT_INDEX(5) |
>> + event_flags;
>> +
>> + if (is_mec) {
>> + radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 5, 0));
>> + radeon_emit(cs, op);
>> + radeon_emit(cs, EOP_DATA_SEL(data_sel));
>> + radeon_emit(cs, va); /* address lo */
>> + radeon_emit(cs, va >> 32); /* address hi */
>> + radeon_emit(cs, new_fence); /* immediate data lo */
>> + radeon_emit(cs, 0); /* immediate data hi */
>> + } else {
>> + if (chip_class == CIK ||
>> + chip_class == VI) {
>> + /* Two EOP events are required to make all engines
>> go idle
>> + * (and optional cache flushes executed) before the
>> timstamp
>> + * is written.
>> + */
>> + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
>> + radeon_emit(cs, op);
>> + radeon_emit(cs, va);
>> + radeon_emit(cs, ((va >> 32) & 0xffff) |
>> EOP_DATA_SEL(data_sel));
>> + radeon_emit(cs, old_fence); /* immediate data */
>> + radeon_emit(cs, 0); /* unused */
>> + }
>> +
>> + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
>> + radeon_emit(cs, op);
>> + radeon_emit(cs, va);
>> + radeon_emit(cs, ((va >> 32) & 0xffff) |
>> EOP_DATA_SEL(data_sel));
>> + radeon_emit(cs, new_fence); /* immediate data */
>> + radeon_emit(cs, 0); /* unused */
>> + }
>> +}
>> +
>> void
>> si_emit_wait_fence(struct radeon_winsys_cs *cs,
>> uint64_t va, uint32_t ref,
>> --
>> 2.9.3
>>
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