Resident buffers have to be added to every new command stream.
Though, this could be slightly improved when current shaders
don't use any bindless textures/images but usually applications
tend to use bindless for almost every draw call, and the winsys
thread might help when buffers are added early.
v2: - store pipe_sampler_view instead of si_sampler_view
Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
---
src/gallium/drivers/radeonsi/si_descriptors.c | 50 +++++++++++++++++++++++++++
src/gallium/drivers/radeonsi/si_hw_context.c | 1 +
src/gallium/drivers/radeonsi/si_state.h | 1 +
3 files changed, 52 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 238cca4561..769ce778cf 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -2373,6 +2373,56 @@ static void si_make_image_handle_resident(struct
pipe_context *ctx,
}
+void si_all_resident_buffers_begin_new_cs(struct si_context *sctx)
+{
+ unsigned num_resident_tex_handles, num_resident_img_handles;
+ unsigned num_bindless_descriptors;
+ unsigned i;
+
+ num_resident_tex_handles = sctx->resident_tex_handles.size /
+ sizeof(struct si_texture_handle *);
+ num_resident_img_handles = sctx->resident_img_handles.size /
+ sizeof(struct si_image_handle *);
+ num_bindless_descriptors = sctx->bindless_descriptors.size /
+ sizeof(struct r600_resource *);
+
+ /* Add all bindless descriptors. */
+ for (i = 0; i < num_bindless_descriptors; i++) {
+ struct r600_resource *desc =
+ *util_dynarray_element(&sctx->bindless_descriptors,
+ struct r600_resource *, i);
+
+ radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc,
+ RADEON_USAGE_READ,
+ RADEON_PRIO_DESCRIPTORS);
+ }
+
+ /* Add all resident texture handles. */
+ for (i = 0; i < num_resident_tex_handles; i++) {
+ struct si_texture_handle *tex_handle =
+ *util_dynarray_element(&sctx->resident_tex_handles,
+ struct si_texture_handle *, i);
+ struct si_sampler_view *sview =
+ (struct si_sampler_view *)tex_handle->view;
+
+ si_sampler_view_add_buffer(sctx, sview->base.texture,
+ RADEON_USAGE_READ,
+ sview->is_stencil_sampler, false);
+ }
+
+ /* Add all resident image handles. */
+ for (i = 0; i < num_resident_img_handles; i++) {
+ struct si_image_handle *img_handle =
+ *util_dynarray_element(&sctx->resident_img_handles,
+ struct si_image_handle *, i);
+ struct pipe_image_view *view = &img_handle->view;
+
+ si_sampler_view_add_buffer(sctx, view->resource,
+ RADEON_USAGE_READWRITE,
+ false, false);
+ }
+}
+
/* INIT/DEINIT/UPLOAD */
/* GFX9 has only 4KB of CE, while previous chips had 32KB. In order
diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c
b/src/gallium/drivers/radeonsi/si_hw_context.c
index 92c09cb633..345825af00 100644
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -235,6 +235,7 @@ void si_begin_new_cs(struct si_context *ctx)
si_mark_atom_dirty(ctx, &ctx->b.streamout.enable_atom);
si_mark_atom_dirty(ctx, &ctx->b.render_cond_atom);
si_all_descriptors_begin_new_cs(ctx);
+ si_all_resident_buffers_begin_new_cs(ctx);
ctx->b.scissors.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
ctx->b.viewports.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
diff --git a/src/gallium/drivers/radeonsi/si_state.h
b/src/gallium/drivers/radeonsi/si_state.h
index d780777ad1..24b5ca33fd 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -323,6 +323,7 @@ bool si_upload_graphics_shader_descriptors(struct
si_context *sctx);
bool si_upload_compute_shader_descriptors(struct si_context *sctx);
void si_release_all_descriptors(struct si_context *sctx);
void si_all_descriptors_begin_new_cs(struct si_context *sctx);
+void si_all_resident_buffers_begin_new_cs(struct si_context *sctx);
void si_upload_const_buffer(struct si_context *sctx, struct r600_resource
**rbuffer,
const uint8_t *ptr, unsigned size, uint32_t
*const_offset);
void si_update_all_texture_descriptors(struct si_context *sctx);
--
2.13.0
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