From: Daniel Stone <dani...@collabora.com>
When importing a dmabuf, verify that the tiling mode matches what was
expected.
Signed-off-by: Daniel Stone <dani...@collabora.com>
Signed-off-by: Varad Gautam <varadgau...@gmail.com>
---
src/mesa/drivers/dri/i965/brw_bufmgr.c | 12 ++++++++++--
src/mesa/drivers/dri/i965/brw_bufmgr.h | 3 ++-
src/mesa/drivers/dri/i965/intel_screen.c | 10 ++++++----
3 files changed, 18 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index 2f17934..56cf979 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -1014,7 +1014,7 @@ brw_bo_get_tiling(struct brw_bo *bo, uint32_t
*tiling_mode,
struct brw_bo *
brw_bo_gem_create_from_prime(struct brw_bufmgr *bufmgr, int prime_fd,
- int size)
+ int size, uint32_t tiling)
{
int ret;
uint32_t handle;
@@ -1071,8 +1071,16 @@ brw_bo_gem_create_from_prime(struct brw_bufmgr *bufmgr,
int prime_fd,
if (drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling))
goto err;
- bo->tiling_mode = get_tiling.tiling_mode;
bo->swizzle_mode = get_tiling.swizzle_mode;
+ bo->tiling_mode = get_tiling.tiling_mode;
+
+ /* If the import explicitly specifies a tiling mode, verify that it matches;
+ * TILING_X is taken as the default where a mismatch is not fatal, and means
+ * to infer the real tiling mode. */
+ if (tiling != I915_TILING_X &&
+ (bo->tiling_mode != tiling && bo->tiling_mode != I915_TILING_NONE))
+ goto err;
+
/* XXX stride is unknown */
out:
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index 56ec206..0a85d9d 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -272,7 +272,8 @@ void brw_destroy_hw_context(struct brw_bufmgr *bufmgr,
uint32_t ctx_id);
int brw_bo_gem_export_to_prime(struct brw_bo *bo, int *prime_fd);
struct brw_bo *brw_bo_gem_create_from_prime(struct brw_bufmgr *bufmgr,
- int prime_fd, int size);
+ int prime_fd, int size,
+ uint32_t tiling);
int brw_reg_read(struct brw_bufmgr *bufmgr, uint32_t offset,
uint64_t *result);
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/mesa/drivers/dri/i965/intel_screen.c
index 4fd6d17..857983d 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -929,6 +929,7 @@ intel_create_image_from_fds(__DRIscreen *dri_screen,
struct intel_image_format *f;
__DRIimage *image;
struct brw_bo *bo;
+ uint32_t tiling = I915_TILING_X; /* default to X-tiling */
int i, index, size = 0;
if (fds == NULL || num_fds < 1)
@@ -948,9 +949,10 @@ intel_create_image_from_fds(__DRIscreen *dri_screen,
/* We only support all planes from the same bo.
* brw_bo_gem_create_from_prime() should return the same pointer for all
* fds received here */
- bo = brw_bo_gem_create_from_prime(screen->bufmgr, fds[0], size);
+ bo = brw_bo_gem_create_from_prime(screen->bufmgr, fds[0], size, tiling);
for (i = 1; i < num_fds; i++) {
- if (bo != brw_bo_gem_create_from_prime(screen->bufmgr, fds[i], size))
+ if (bo != brw_bo_gem_create_from_prime(screen->bufmgr, fds[i],
+ size, tiling))
return NULL;
}
@@ -981,8 +983,8 @@ intel_create_image_from_fds(__DRIscreen *dri_screen,
size = end;
}
- image->bo = brw_bo_gem_create_from_prime(screen->bufmgr,
- fds[0], size);
+ image->bo = brw_bo_gem_create_from_prime(screen->bufmgr, fds[0], size,
+ tiling);
if (image->bo == NULL) {
free(image);
return NULL;
--
2.10.0
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