---
src/mesa/drivers/dri/i965/brw_clear.c | 12 ++++++++++--
src/mesa/drivers/dri/i965/brw_draw.c | 12 +++++++++++-
src/mesa/drivers/dri/i965/intel_fbo.c | 15 ---------------
src/mesa/drivers/dri/i965/intel_fbo.h | 3 ---
4 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c
b/src/mesa/drivers/dri/i965/brw_clear.c
index adaf250..9f4a7e6 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -207,7 +207,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
}
- if (fb->MaxNumLayers > 0) {
+ if (depth_att->Layered) {
for (unsigned layer = 0; layer < depth_irb->layer_count; layer++) {
intel_hiz_exec(brw, mt, depth_irb->mt_level,
depth_irb->mt_layer + layer,
@@ -236,7 +236,15 @@ brw_fast_clear_depth(struct gl_context *ctx)
/* Now, the HiZ buffer contains data that needs to be resolved to the depth
* buffer.
*/
- intel_renderbuffer_att_set_needs_depth_resolve(depth_att);
+ if (fb->MaxNumLayers > 0) {
+ for (unsigned layer = 0; layer < depth_irb->layer_count; layer++) {
+ intel_miptree_slice_set_needs_depth_resolve(mt, depth_irb->mt_level,
+ depth_irb->mt_layer +
layer);
+ }
+ } else {
+ intel_miptree_slice_set_needs_depth_resolve(mt, depth_irb->mt_level,
+ depth_irb->mt_layer);
+ }
return true;
}
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index 23a3c6c..f728731 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -373,7 +373,17 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context
*brw)
if (back_irb)
back_irb->need_downsample = true;
if (depth_irb && brw_depth_writes_enabled(brw)) {
- intel_renderbuffer_att_set_needs_depth_resolve(depth_att);
+ if (depth_att->Layered) {
+ for (unsigned layer = 0; layer < depth_irb->layer_count; layer++) {
+ intel_miptree_slice_set_needs_depth_resolve(depth_irb->mt,
+ depth_irb->mt_level,
+ depth_irb->mt_layer +
layer);
+ }
+ } else {
+ intel_miptree_slice_set_needs_depth_resolve(depth_irb->mt,
+ depth_irb->mt_level,
+ depth_irb->mt_layer);
+ }
brw_render_cache_set_add_bo(brw, depth_irb->mt->bo);
}
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c
b/src/mesa/drivers/dri/i965/intel_fbo.c
index b200417..d8eb890 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -944,21 +944,6 @@ intel_renderbuffer_has_hiz(struct intel_renderbuffer *irb)
}
void
-intel_renderbuffer_att_set_needs_depth_resolve(struct
gl_renderbuffer_attachment *att)
-{
- struct intel_renderbuffer *irb = intel_renderbuffer(att->Renderbuffer);
- if (irb->mt) {
- if (att->Layered) {
- intel_miptree_set_all_slices_need_depth_resolve(irb->mt,
irb->mt_level);
- } else {
- intel_miptree_slice_set_needs_depth_resolve(irb->mt,
- irb->mt_level,
- irb->mt_layer);
- }
- }
-}
-
-void
intel_renderbuffer_move_to_temp(struct brw_context *brw,
struct intel_renderbuffer *irb,
bool invalidate)
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.h
b/src/mesa/drivers/dri/i965/intel_fbo.h
index 7f2e3b3..116f385 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.h
+++ b/src/mesa/drivers/dri/i965/intel_fbo.h
@@ -195,9 +195,6 @@ intel_renderbuffer_get_tile_offsets(struct
intel_renderbuffer *irb,
bool
intel_renderbuffer_has_hiz(struct intel_renderbuffer *irb);
-void
-intel_renderbuffer_att_set_needs_depth_resolve(struct
gl_renderbuffer_attachment *att);
-
void intel_renderbuffer_move_to_temp(struct brw_context *brw,
struct intel_renderbuffer *irb,
--
2.5.0.400.gff86faf
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