This patch:
Reviewed-by: Marek Olšák <marek.ol...@amd.com>
Marek
On Thu, May 18, 2017 at 11:53 AM, Nicolai Hähnle <nhaeh...@gmail.com> wrote:
> From: Nicolai Hähnle <nicolai.haeh...@amd.com>
>
> This is needed by radv for dEQP-VK.renderpass.simple.stencil
> ---
> src/amd/common/ac_surface.c | 75
> ++++++++++++++++++++++++++++++---------------
> 1 file changed, 50 insertions(+), 25 deletions(-)
>
> diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
> index d77b490..51e15d0 100644
> --- a/src/amd/common/ac_surface.c
> +++ b/src/amd/common/ac_surface.c
> @@ -380,20 +380,45 @@ static unsigned cik_get_macro_tile_index(struct
> radeon_surf *surf)
> tileb = MIN2(surf->u.legacy.tile_split, tileb);
>
> for (index = 0; tileb > 64; index++)
> tileb >>= 1;
>
> assert(index < 16);
> return index;
> }
>
> /**
> + * Copy surface-global settings like pipe/bank config from level 0 surface
> + * computation.
> + */
> +static void gfx6_surface_settings(const struct radeon_info* info,
> + ADDR_COMPUTE_SURFACE_INFO_OUTPUT* csio,
> + struct radeon_surf *surf)
> +{
> + surf->surf_alignment = csio->baseAlign;
> + surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
> + gfx6_set_micro_tile_mode(surf, info);
> +
> + /* For 2D modes only. */
> + if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) {
> + surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
> + surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
> + surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
> + surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
> + surf->u.legacy.num_banks = csio->pTileInfo->banks;
> + surf->u.legacy.macro_tile_index = csio->macroModeIndex;
> + } else {
> + surf->u.legacy.macro_tile_index = 0;
> + }
> +}
> +
> +/**
> * Fill in the tiling information in \p surf based on the given surface
> config.
> *
> * The following fields of \p surf must be initialized by the caller:
> * blk_w, blk_h, bpe, flags.
> */
> static int gfx6_compute_surface(ADDR_HANDLE addrlib,
> const struct radeon_info *info,
> const struct ac_surf_config *config,
> enum radeon_surf_mode mode,
> struct radeon_surf *surf)
> @@ -577,44 +602,36 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
> }
>
> surf->num_dcc_levels = 0;
> surf->surf_size = 0;
> surf->dcc_size = 0;
> surf->dcc_alignment = 1;
> surf->htile_size = 0;
> surf->htile_slice_size = 0;
> surf->htile_alignment = 1;
>
> + const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
> + !(surf->flags & RADEON_SURF_ZBUFFER);
> +
> /* Calculate texture layout information. */
> - for (level = 0; level < config->info.levels; level++) {
> - r = gfx6_compute_level(addrlib, config, surf, false, level,
> compressed,
> - &AddrSurfInfoIn, &AddrSurfInfoOut,
> - &AddrDccIn, &AddrDccOut, &AddrHtileIn,
> &AddrHtileOut);
> - if (r)
> - return r;
> + if (!only_stencil) {
> + for (level = 0; level < config->info.levels; level++) {
> + r = gfx6_compute_level(addrlib, config, surf, false,
> level, compressed,
> + &AddrSurfInfoIn,
> &AddrSurfInfoOut,
> + &AddrDccIn, &AddrDccOut,
> &AddrHtileIn, &AddrHtileOut);
> + if (r)
> + return r;
>
> - if (level == 0) {
> - surf->surf_alignment = AddrSurfInfoOut.baseAlign;
> - surf->u.legacy.pipe_config =
> AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
> - gfx6_set_micro_tile_mode(surf, info);
> -
> - /* For 2D modes only. */
> - if (AddrSurfInfoOut.tileMode >=
> ADDR_TM_2D_TILED_THIN1) {
> - surf->u.legacy.bankw =
> AddrSurfInfoOut.pTileInfo->bankWidth;
> - surf->u.legacy.bankh =
> AddrSurfInfoOut.pTileInfo->bankHeight;
> - surf->u.legacy.mtilea =
> AddrSurfInfoOut.pTileInfo->macroAspectRatio;
> - surf->u.legacy.tile_split =
> AddrSurfInfoOut.pTileInfo->tileSplitBytes;
> - surf->u.legacy.num_banks =
> AddrSurfInfoOut.pTileInfo->banks;
> - surf->u.legacy.macro_tile_index =
> AddrSurfInfoOut.macroModeIndex;
> - } else {
> - surf->u.legacy.macro_tile_index = 0;
> - }
> + if (level > 0)
> + continue;
> +
> + gfx6_surface_settings(info, &AddrSurfInfoOut, surf);
> }
> }
>
> /* Calculate texture layout information for stencil. */
> if (surf->flags & RADEON_SURF_SBUFFER) {
> AddrSurfInfoIn.bpp = 8;
> AddrSurfInfoIn.flags.depth = 0;
> AddrSurfInfoIn.flags.stencil = 1;
> AddrSurfInfoIn.flags.tcCompatible = 0;
> /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL.
> */
> @@ -622,25 +639,33 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
>
> for (level = 0; level < config->info.levels; level++) {
> r = gfx6_compute_level(addrlib, config, surf, true,
> level, compressed,
> &AddrSurfInfoIn,
> &AddrSurfInfoOut,
> &AddrDccIn, &AddrDccOut,
> NULL, NULL);
> if (r)
> return r;
>
> /* DB uses the depth pitch for both stencil and
> depth. */
> - if (surf->u.legacy.stencil_level[level].nblk_x !=
> - surf->u.legacy.level[level].nblk_x)
> - surf->u.legacy.stencil_adjusted = true;
> + if (!only_stencil) {
> + if
> (surf->u.legacy.stencil_level[level].nblk_x !=
> + surf->u.legacy.level[level].nblk_x)
> + surf->u.legacy.stencil_adjusted =
> true;
> + } else {
> + surf->u.legacy.level[level].nblk_x =
> +
> surf->u.legacy.stencil_level[level].nblk_x;
> + }
>
> if (level == 0) {
> + if (only_stencil)
> + gfx6_surface_settings(info,
> &AddrSurfInfoOut, surf);
> +
> /* For 2D modes only. */
> if (AddrSurfInfoOut.tileMode >=
> ADDR_TM_2D_TILED_THIN1) {
> surf->u.legacy.stencil_tile_split =
>
> AddrSurfInfoOut.pTileInfo->tileSplitBytes;
> }
> }
> }
> }
>
> /* Recalculate the whole DCC miptree size including disabled levels.
> --
> 2.9.3
>
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