Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/brw_blorp.c | 11 +++-
src/mesa/drivers/dri/i965/brw_tex_layout.c | 56 ------------------
src/mesa/drivers/dri/i965/gen6_depth_state.c | 18 +++---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 84 ++++-----------------------
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 12 ----
5 files changed, 27 insertions(+), 154 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index c0aa139..0235681 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -241,9 +241,14 @@ blorp_surf_for_miptree(struct brw_context *brw,
/* gen6 requires the HiZ buffer to be manually offset to the
* right location.
*/
- surf->aux_addr.offset = brw_hiz_all_slices_at_each_lod_offset(
- &surf->surf->phys_level0_sa, surf->surf->dim,
- surf->surf->levels, surf->surf->format, *level);
+ uint32_t x_offset_sa, y_offset_sa;
+ get_image_offset_sa_gen6_back_to_back(&mt->hiz_buf->surf,
+ *level, 0, 0,
+ &x_offset_sa, &y_offset_sa);
+ assert(x_offset_sa == 0);
+
+ surf->aux_addr.offset = y_offset_sa * mt->hiz_buf->surf.row_pitch;
+ assert(surf->aux_addr.offset % 4096 == 0);
/* In depth state setup only surf->aux_surf.row_pitch gets
* consulted. Otherwise surf->aux_surf is ignored and there is
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index b58a846..deac692 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -236,62 +236,6 @@ brw_get_mipmap_total_width(unsigned w0, unsigned
num_levels, unsigned halign)
return ALIGN(MAX2(w0, w1 + w2), halign);
}
-uint32_t
-brw_hiz_all_slices_at_each_lod_offset(
- const struct isl_extent4d *phys_level0_sa,
- enum isl_surf_dim dim, unsigned num_levels,
- enum isl_format format, unsigned level)
-{
- const uint32_t cpp = isl_format_get_layout(format)->bpb / 8;
- const uint32_t halign = 128 / cpp;
- const uint32_t valign = 32;
- const uint32_t level_x = all_slices_at_each_lod_x_offset(
- phys_level0_sa->width, halign, level);
- const uint32_t level_y = all_slices_at_each_lod_y_offset(
- phys_level0_sa, dim, valign, level);
- const uint32_t pitch = brw_get_mipmap_total_width(
- phys_level0_sa->width, num_levels, halign) * cpp;
-
- return level_y * pitch + level_x / halign * 4096;
-}
-
-uint32_t
-brw_all_slices_at_each_lod_total_height(
- const struct isl_extent4d *phys_level0_sa,
- enum isl_surf_dim dim, isl_surf_usage_flags_t usage,
- unsigned last_level, unsigned valign)
-{
- /* The 965's sampler lays cachelines out according to how accesses
- * in the texture surfaces run, so they may be "vertical" through
- * memory. As a result, the docs say in Surface Padding Requirements:
- * Sampling Engine Surfaces that two extra rows of padding are required.
- */
- const unsigned extra_padding = usage & ISL_SURF_USAGE_CUBE_BIT ? 2 : 0;
- const unsigned second_level_y = all_slices_at_each_lod_y_offset(
- phys_level0_sa, dim, valign, 1);
-
- /* Second level would be just below first, and its start position is equal
- * to the aligned size needed for the the first.
- */
- if (last_level == 0)
- return second_level_y + extra_padding;
-
- const unsigned last_level_y = all_slices_at_each_lod_y_offset(
- phys_level0_sa, dim, valign, last_level);
- const unsigned second_level_h =
- phys_level0_sa->array_len *
- ALIGN(minify(phys_level0_sa->height, 1), valign);
- const unsigned last_level_h =
- phys_level0_sa->array_len *
- ALIGN(minify(phys_level0_sa->height, last_level), valign);
-
- /* Choose the taller of the two: end of the second or end of the last. */
- const unsigned total_h = MAX2(second_level_y + second_level_h,
- last_level_y + last_level_h);
-
- return ALIGN(total_h, valign) + extra_padding;
-}
-
static void
brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
{
diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c
b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index e057c3e..16fb209 100644
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -162,15 +162,15 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
if (hiz) {
assert(depth_mt);
- struct isl_surf temp_surf;
- intel_miptree_get_isl_surf(brw, mt, &temp_surf);
-
- /* Main and hiz surfaces agree on the base level dimensions and
- * format. Therefore one can calculate against the main surface.
- */
- const uint32_t offset = brw_hiz_all_slices_at_each_lod_offset(
- &temp_surf.phys_level0_sa, temp_surf.dim, temp_surf.levels,
- temp_surf.format, lod);
+ uint32_t x_offset_sa, y_offset_sa;
+ get_image_offset_sa_gen6_back_to_back(&depth_mt->hiz_buf->surf,
+ lod, 0, 0,
+ &x_offset_sa, &y_offset_sa);
+ assert(x_offset_sa == 0);
+
+ const uint32_t offset = y_offset_sa *
+ depth_mt->hiz_buf->surf.row_pitch;
+ assert(offset % 4096 == 0);
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 82ffd11..d80a1b6 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -284,61 +284,6 @@ intel_depth_format_for_depthstencil_format(mesa_format
format) {
}
}
-static struct intel_miptree_aux_buffer *
-all_slices_at_each_lod_aux_create(struct brw_context *brw,
- const struct intel_mipmap_tree *mt,
- unsigned halign_bytes, unsigned valign,
- uint32_t tiling, const char *name)
-{
- const uint32_t format = translate_tex_format(brw, mt->format, false);
- const unsigned cpp = isl_format_get_layout(format)->bpb / 8;
- const unsigned halign = halign_bytes / cpp;
- const enum isl_surf_dim dim = get_isl_surf_dim(mt->target);
- const struct isl_extent4d phys_level0_sa = {
- { mt->physical_width0 },
- { mt->physical_height0 },
- { dim == ISL_SURF_DIM_3D ? mt->physical_depth0 : 1 },
- { dim == ISL_SURF_DIM_3D ? 1 : mt->physical_depth0 } };
- const isl_surf_usage_flags_t usage =
- mt->target == GL_TEXTURE_CUBE_MAP ? ISL_SURF_USAGE_CUBE_BIT : 0;
- const unsigned total_h = brw_all_slices_at_each_lod_total_height(
- &phys_level0_sa, dim, usage, mt->last_level, valign);
- const unsigned total_w = brw_get_mipmap_total_width(
- phys_level0_sa.width, mt->last_level + 1, halign);
-
- struct intel_miptree_aux_buffer *buf = calloc(sizeof(*buf), 1);
- if (!buf)
- return NULL;
-
- buf->pitch = total_w * cpp;
- buf->size = total_h * buf->pitch;
-
- /* On gen6 hiz is unconditionally laid out packing all slices
- * at each level-of-detail (LOD). This means there is no valid qpitch
- * setting. In fact, this is ignored when hardware is setup - there is no
- * hardware qpitch setting of hiz on gen6.
- */
- buf->qpitch = 0;
-
- /* Blorp depth state setup relies on ISL surface. Fortunately only
- * ::row_pitch gets consulted while the rest gets ignored.
- * See blorp_emit_depth_stencil_config().
- */
- buf->surf.row_pitch = buf->pitch;
-
- unsigned pitch = buf->pitch;
- buf->bo = brw_bo_alloc_tiled(brw->bufmgr, name, total_w, total_h, cpp,
- tiling, &pitch, BO_ALLOC_FOR_RENDER);
- if (!buf->bo) {
- free(buf);
- return NULL;
- }
-
- assert(pitch == buf->pitch);
-
- return buf;
-}
-
/**
* @param for_bo Indicates that the caller is
* intel_miptree_create_for_bo(). If true, then do not create
@@ -1648,28 +1593,19 @@ intel_miptree_alloc_hiz(struct brw_context *brw,
assert(mt->hiz_buf == NULL);
assert((mt->aux_disable & INTEL_AUX_DISABLE_HIZ) == 0);
- if (brw->gen == 6) {
- const unsigned halign_bytes = 128;
- const unsigned valign = 32;
- uint32_t tiling = I915_TILING_Y;
- mt->hiz_buf = all_slices_at_each_lod_aux_create(brw, mt, halign_bytes,
- valign, tiling, "hiz");
- } else {
- struct isl_surf temp_main_surf;
- struct isl_surf temp_hiz_surf;
-
- intel_miptree_get_isl_surf(brw, mt, &temp_main_surf);
- isl_surf_get_hiz_surf(&brw->isl_dev, &temp_main_surf, &temp_hiz_surf);
+ struct isl_surf temp_main_surf;
+ struct isl_surf temp_hiz_surf;
- assert(temp_hiz_surf.size &&
- (temp_hiz_surf.size % temp_hiz_surf.row_pitch == 0));
+ intel_miptree_get_isl_surf(brw, mt, &temp_main_surf);
+ isl_surf_get_hiz_surf(&brw->isl_dev, &temp_main_surf, &temp_hiz_surf);
- const uint32_t alloc_flags = BO_ALLOC_FOR_RENDER;
- mt->hiz_buf = intel_alloc_aux_buffer(brw, "hiz-miptree",
- &temp_main_surf, &temp_hiz_surf,
- alloc_flags, mt);
- }
+ assert(temp_hiz_surf.size &&
+ (temp_hiz_surf.size % temp_hiz_surf.row_pitch == 0));
+ const uint32_t alloc_flags = BO_ALLOC_FOR_RENDER;
+ mt->hiz_buf = intel_alloc_aux_buffer(brw, "hiz-miptree",
+ &temp_main_surf, &temp_hiz_surf,
+ alloc_flags, mt);
if (!mt->hiz_buf)
return false;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index dd77621..913fb4c 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -967,18 +967,6 @@ uint32_t
brw_stencil_all_slices_at_each_lod_offset(const struct isl_surf *surf,
uint32_t level);
-uint32_t
-brw_hiz_all_slices_at_each_lod_offset(
- const struct isl_extent4d *phys_level0_sa,
- enum isl_surf_dim dim, unsigned num_levels,
- enum isl_format format, unsigned level);
-
-uint32_t
-brw_all_slices_at_each_lod_total_height(
- const struct isl_extent4d *phys_level0_sa,
- enum isl_surf_dim dim, isl_surf_usage_flags_t usage,
- unsigned last_level, unsigned valign);
-
bool
brw_miptree_layout(struct brw_context *brw,
struct intel_mipmap_tree *mt,
--
2.9.3
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
