While gen >= 8 can sample w-tiled stencil surfaces just fine, this
option allows testing of the legacy behavior even on gen8+.
Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/intel/blorp/blorp.c | 4 +++-
src/intel/blorp/blorp_blit.c | 9 +++++++--
src/intel/common/gen_debug.c | 1 +
src/intel/common/gen_debug.h | 1 +
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 5 +++--
src/mesa/drivers/dri/i965/gen8_depth_state.c | 3 +++
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 10 +++++++++-
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 +++
8 files changed, 30 insertions(+), 6 deletions(-)
diff --git a/src/intel/blorp/blorp.c b/src/intel/blorp/blorp.c
index 0b2395d..14a13f3 100644
--- a/src/intel/blorp/blorp.c
+++ b/src/intel/blorp/blorp.c
@@ -28,6 +28,7 @@
#include "blorp_priv.h"
#include "compiler/brw_compiler.h"
#include "compiler/brw_nir.h"
+#include "common/gen_debug.h"
void
blorp_init(struct blorp_context *blorp, void *driver_ctx,
@@ -84,7 +85,8 @@ brw_blorp_surface_info_init(struct blorp_context *blorp,
} else if (surf->surf->usage & ISL_SURF_USAGE_STENCIL_BIT) {
assert(surf->surf->format == ISL_FORMAT_R8_UINT);
/* Prior to Broadwell, we can't render to R8_UINT */
- if (blorp->isl_dev->info->gen < 8)
+ if (blorp->isl_dev->info->gen < 8 ||
+ unlikely(INTEL_DEBUG & DEBUG_R8_STENCIL))
format = ISL_FORMAT_R8_UNORM;
}
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index 691564c..8e3fc31 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -22,6 +22,7 @@
*/
#include "compiler/nir/nir_builder.h"
+#include "common/gen_debug.h"
#include "blorp_priv.h"
@@ -1111,7 +1112,9 @@ brw_blorp_build_nir_shader(struct blorp_context *blorp,
void *mem_ctx,
/* Render target and texture hardware don't support W tiling until Gen8. */
const bool rt_tiled_w = false;
- const bool tex_tiled_w = devinfo->gen >= 8 && key->src_tiled_w;
+ const bool can_sample_w_tiled =
+ devinfo->gen >= 8 && !unlikely(INTEL_DEBUG & DEBUG_R8_STENCIL);
+ const bool tex_tiled_w = can_sample_w_tiled && key->src_tiled_w;
/* The address that data will be written to is determined by the
* coordinates supplied to the WM thread and the tiling and sample count of
@@ -1766,7 +1769,9 @@ try_blorp_blit(struct blorp_batch *batch,
}
}
- if (devinfo->gen < 8 && params->src.surf.tiling == ISL_TILING_W) {
+ const bool needs_y_tiled_stencil =
+ devinfo->gen <= 7 || unlikely(INTEL_DEBUG & DEBUG_R8_STENCIL);
+ if (needs_y_tiled_stencil && params->src.surf.tiling == ISL_TILING_W) {
/* On Haswell and earlier, we have to fake W-tiled sources as Y-tiled.
* Broadwell adds support for sampling from stencil.
*
diff --git a/src/intel/common/gen_debug.c b/src/intel/common/gen_debug.c
index be6fcdb..48aefc3 100644
--- a/src/intel/common/gen_debug.c
+++ b/src/intel/common/gen_debug.c
@@ -84,6 +84,7 @@ static const struct debug_control debug_control[] = {
{ "norbc", DEBUG_NO_RBC },
{ "nohiz", DEBUG_NO_HIZ },
{ "color", DEBUG_COLOR },
+ { "r8_stencil", DEBUG_R8_STENCIL},
{ NULL, 0 }
};
diff --git a/src/intel/common/gen_debug.h b/src/intel/common/gen_debug.h
index c0b74ea..582fd5b 100644
--- a/src/intel/common/gen_debug.h
+++ b/src/intel/common/gen_debug.h
@@ -82,6 +82,7 @@ extern uint64_t INTEL_DEBUG;
#define DEBUG_NO_RBC (1ull << 38)
#define DEBUG_NO_HIZ (1ull << 39)
#define DEBUG_COLOR (1ull << 40)
+#define DEBUG_R8_STENCIL (1ull << 41)
#ifdef HAVE_ANDROID_PLATFORM
#define LOG_TAG "INTEL-MESA"
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 49383c7..6b078c0 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -597,14 +597,15 @@ brw_update_texture_surface(struct gl_context *ctx,
}
if (obj->StencilSampling && firstImage->_BaseFormat == GL_DEPTH_STENCIL)
{
- if (brw->gen <= 7) {
+ if (intel_miptree_wants_r8_stencil(brw)) {
assert(mt->r8stencil_mt &&
!mt->stencil_mt->r8stencil_needs_update);
mt = mt->r8stencil_mt;
} else {
mt = mt->stencil_mt;
}
format = ISL_FORMAT_R8_UINT;
- } else if (brw->gen <= 7 && mt->format == MESA_FORMAT_S_UINT8) {
+ } else if (intel_miptree_wants_r8_stencil(brw) &&
+ mt->format == MESA_FORMAT_S_UINT8) {
assert(mt->r8stencil_mt && !mt->r8stencil_needs_update);
mt = mt->r8stencil_mt;
format = ISL_FORMAT_R8_UINT;
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c
b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index 2a19b79..6105c3e 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -110,6 +110,9 @@ emit_depth_packets(struct brw_context *brw,
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
+ if (intel_miptree_wants_r8_stencil(brw))
+ stencil_mt->r8stencil_needs_update = true;
+
BEGIN_BATCH(5);
OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (5 - 2));
/* The stencil buffer has quirky pitch requirements. From the Graphics
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index db0a397..54ef1ba 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1850,6 +1850,12 @@ intel_miptree_wants_hiz_buffer(struct brw_context *brw,
}
bool
+intel_miptree_wants_r8_stencil(const struct brw_context *brw)
+{
+ return brw->gen <= 7 || unlikely(INTEL_DEBUG & DEBUG_R8_STENCIL);
+}
+
+bool
intel_miptree_alloc_hiz(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
@@ -2372,7 +2378,9 @@ intel_update_r8stencil(struct brw_context *brw,
assert(brw->gen >= 7);
struct intel_mipmap_tree *src =
mt->format == MESA_FORMAT_S_UINT8 ? mt : mt->stencil_mt;
- if (!src || brw->gen >= 8 || !src->r8stencil_needs_update)
+ if (!src ||
+ !intel_miptree_wants_r8_stencil(brw) ||
+ !src->r8stencil_needs_update)
return;
if (!mt->r8stencil_mt) {
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 7aabac0..4bc30a2 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -834,6 +834,9 @@ bool
intel_miptree_wants_hiz_buffer(struct brw_context *brw,
struct intel_mipmap_tree *mt);
+bool
+intel_miptree_wants_r8_stencil(const struct brw_context *brw);
+
/**
* \brief Allocate the miptree's embedded HiZ miptree.
* \see intel_mipmap_tree:hiz_mt
--
2.9.3
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