On 12/06/2011 02:00 PM, Christoph Bumiller wrote:
On 12/06/2011 10:19 AM, Thomas Hellstrom wrote:
Some hardware can't reinterpret the format of hardware buffers and thus
the X server needs to know the format when the buffer is created.

Signed-off-by: Thomas Hellstrom<thellst...@vmware.com>
---
  src/gallium/state_trackers/dri/drm/dri2.c |   43 +++++++++++++++++++++++++++--
  1 files changed, 40 insertions(+), 3 deletions(-)

diff --git a/src/gallium/state_trackers/dri/drm/dri2.c 
b/src/gallium/state_trackers/dri/drm/dri2.c
index 4e3f106..1aab749 100644
--- a/src/gallium/state_trackers/dri/drm/dri2.c
+++ b/src/gallium/state_trackers/dri/drm/dri2.c
@@ -104,7 +104,7 @@ dri2_drawable_get_buffers(struct dri_drawable *drawable,
     for (i = 0; i<  *count; i++) {
        enum pipe_format format;
        unsigned bind;
-      int att, bpp;
+      int att, depth;

        dri_drawable_get_format(drawable, statts[i],&format,&bind);
        if (format == PIPE_FORMAT_NONE)
@@ -134,12 +134,49 @@ dri2_drawable_get_buffers(struct dri_drawable *drawable,
           break;
        }

-      bpp = util_format_get_blocksizebits(format);
+      /*
+       * In this switch statement we must support all formats that
+       * may occur as the stvis->color_format or stvis->
+       *
+       */
+
+
+      switch(format) {
+      case PIPE_FORMAT_B8G8R8A8_UNORM:
+        depth = 32;
+        break;
+      case PIPE_FORMAT_B8G8R8X8_UNORM:
+        depth = 24;
+        break;
+      case PIPE_FORMAT_B5G6R5_UNORM:
+        depth = 16;
+        break;
+      case PIPE_FORMAT_Z16_UNORM:
+        att = __DRI_BUFFER_DEPTH;
+        depth = 16;
+        break;
+      case PIPE_FORMAT_Z24X8_UNORM:
+      case PIPE_FORMAT_X8Z24_UNORM:
+        att = __DRI_BUFFER_DEPTH;
+        depth = 24;
+        break;
+      case PIPE_FORMAT_Z24_UNORM_S8_UINT:
+      case PIPE_FORMAT_S8_UINT_Z24_UNORM:
+        depth = 32;
+        break;
These (Z24S8 vs S8Z24) also can't be reinterpreted among each other by
nv50+, which support both, because they require different flags in the
GPU's page table entries (so the memory controller can play tricks like
storing multiple Z values adjacently in physical memory).

But in practice this is not / hasn't been a problem as long as the
choice remains predictable.

It should be predictable, as long as the X server driver follows the same
algorithm as the dri state tracker when choosing which formats to create
(d_depth_bits_last and sd_depth_bits_last)

/Thomas

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